Molecular Or Atomic Patents (Class 365/151)
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Patent number: 7710768Abstract: A memory element which has high affinity with a conventional semiconductor process, which has a switching function of completely interrupting electric conduction paths by in a mechanical manner, and in which nonvolatile information recording is enabled is realized. An electromechanical memory which is formed on a substrate, which is formed by interposing a memory cell by electrodes, and which has a movable electrode that is a beam stretched in the air via a post portion is realized. According to the configuration, a nonvolatile memory can be realized by a simple structure, and it is possible to realize a high-performance electromechanical memory which is conventionally difficult to be realized, and in which the power consumption is low and the cost is low, and an electric apparatus using it.Type: GrantFiled: June 21, 2006Date of Patent: May 4, 2010Assignee: Panasonic CorporationInventor: Yasuyuki Naito
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Patent number: 7706171Abstract: The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.Type: GrantFiled: August 10, 2007Date of Patent: April 27, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kenichi Murooka
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Patent number: 7705707Abstract: A stack for a bistable microelectronic switch. A porphyrin compound and a conductive polymer are sandwiched between two electrodes. The device exhibits a switching behavior at a certain voltage and can be used in arrays to form a memory device. When a first voltage is applied between the electrodes, the resistance across the two electrodes is very high, and when a increased voltage is applied, the resistance is generally two orders of magnitude lower. Copper phthalocyanine or 5, 10, 15, 20-tetrakis(4-methoxyphenyl)-21H, 23H-porphine cobalt(II) can be used as the bistable compound, and poly-(3,4-ethylenedioxythiophene) and poly-(styrenesulphonic acid) can be used as the conductive polymer.Type: GrantFiled: December 21, 2006Date of Patent: April 27, 2010Assignee: Motorola, Inc.Inventors: Ke K. Lian, John B. Szczech, Jie Zhang
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Patent number: 7701754Abstract: An electromechanical memory cell utilizes a cantilever and a laterally positioned electrode. The cantilever is spaced apart from the electrode by a distance that is greater than the elastic limit of the cantilever. The memory cell is programmed by applying voltages to the cantilever and the electrode which causes the cantilever to move into a region of plastic deformation without ever touching the electrode.Type: GrantFiled: September 5, 2006Date of Patent: April 20, 2010Assignee: National Semiconductor CorporationInventors: Roozbeh Parsa, Trevor Niblock, Mark W. Poulter, Peter J. Hopper
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Patent number: 7695756Abstract: A tool for manufacturing molecular electronic devices having a coating unit contained in a controlled ambient environment. The coating unit is coupled to a source of active device molecules in solution. The coating unit is configured to apply a selected quantity of the solution to a surface of a substrate and the process tool processes the coated substrate in conditions that cause the active device molecules to attach to active areas of the substrate.Type: GrantFiled: April 29, 2004Date of Patent: April 13, 2010Assignee: ZettaCore, Inc.Inventors: Antonio R. Gallo, Werner G. Kuhr
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Publication number: 20100085801Abstract: The invention generally encompasses methods of forming thin films molecular based devices, and devices formed therefrom. Some embodiments relate to molecular memory cells, molecular memory arrays, electronic devices including molecular memory, and processing systems and methods for producing molecular memories. More particularly, the present invention encompasses methods and molecular based devices comprising a wetting layer and redox-active molecules.Type: ApplicationFiled: October 1, 2009Publication date: April 8, 2010Inventors: Thomas A. Sorenson, Brian Eastep, Lee Gaherty, Timothy L. Snow
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Patent number: 7692952Abstract: Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further show how to generate different code permutations through random misalignment and how to promote uniform code probability selection.Type: GrantFiled: August 24, 2004Date of Patent: April 6, 2010Assignee: California Institute of TechnologyInventor: André DeHon
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Patent number: 7692953Abstract: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.Type: GrantFiled: January 16, 2009Date of Patent: April 6, 2010Assignee: STMicroelectronics S.r.l.Inventors: Danilo Mascolo, Gianfranco Cerofolini
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Publication number: 20100073995Abstract: A nano device includes an array of cells disposed in rows and columns and constructed over a substrate, and an optical circuit disposed over the substrate, wherein the optical circuit is formed by nano elements in a self-assembled process.Type: ApplicationFiled: November 12, 2009Publication date: March 25, 2010Inventor: Bao Tran
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Patent number: 7679946Abstract: Disclosed is a memory element array comprising a plurality of memory elements arranged in an array, wherein the memory elements are switching elements each including a gap of nanometer order in which a switching phenomenon of resistance is caused by applying a predetermined voltage between electrodes, and the memory element array is provided with tunnel elements respectively connected to the switching elements in series, each of the tunnel elements preventing generation of a sneak path current flowing to another switching element at a time of applying the predetermined voltage.Type: GrantFiled: June 18, 2008Date of Patent: March 16, 2010Assignees: Funai Electric Advanced Applied Technology Research Institute Inc., Funai Electric Co., Ltd.Inventors: Shigeo Furuta, Yuichiro Masuda, Tsuyoshi Takahashi, Masatoshi Ono
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Patent number: 7679080Abstract: A functional molecular device displaying its functions under the action of an electrical field is provided. A Louis base molecule, exhibiting positive dielectric constant anisotropy or exhibiting dipole moment along the long-axis direction of the Louis base molecule, is arrayed in the form of a pendant on an electrically conductive linear or film-shaped principal-axis molecule of a conjugated system, via a metal ion capable of acting as a Louis acid. The resulting structure is changed in conformation on application of an electrical field to exhibit its function. The electrically conductive linear or film-shaped principal-axis molecule and the Louis base molecule form a complex with the metal ion. On application of the electrical field, the Louis base molecule performs a swinging movement or a seesaw movement to switch the electrical conductivity of the principal-axis molecule.Type: GrantFiled: June 23, 2005Date of Patent: March 16, 2010Assignees: Sony Corporation, Sony Deutschland G.m.b.H.Inventors: Eriko Matsui, Nobuyuki Matsuzawa, Akio Yasuda, Oliver Harnack
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Patent number: 7668004Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.Type: GrantFiled: January 25, 2008Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III
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Patent number: 7660145Abstract: An object of the present invention is to provide nonvolatile, rewritable, easily-manufactured, and inexpensive storage element, storage device, and semiconductor device, which are superior in switching characteristics and which has low operation voltage. In an element including a first conductive layer, a second conductive layer facing the first conductive layer, and a layer containing at least one kind of an organic compound provided between the first conductive layer and the second conductive layer, the organic compound can be electrochemically doped or dedoped. By feeding current in this element, the organic compound provided between the conductive layers is electrochemically doped, i.e., electrons are transported, whereby the conductivity can be increased by about three to ten digits.Type: GrantFiled: June 27, 2006Date of Patent: February 9, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Ryoji Nomura
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Patent number: 7652911Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.Type: GrantFiled: December 10, 2008Date of Patent: January 26, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gregory S. Snider, Philip J. Kuekes
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Patent number: 7638831Abstract: A molecular memory including a substrate made of silicon; a set of condensers, each condenser including two conductive layers constituting armatures of the condensers and between which is placed a dielectric layer; and a connector to provide electric contacts with external circuits, wherein the dielectric layer comprises at least partially a polymer containing triazole derivatives, a spin transition phenomenon support material or a spin transition molecular complex; and a method for manufacturing a molecular memory including covering a substrate with a conductive layer; coating a dielectric material on the conductive layer; covering the dielectric material with the conductive layer; impregnating by immersion a buffer in an inking solution of hexadecanethiol; drying and washing the impregnated buffer; creating a protective monolayer on the conductive layer by application of the impregnated, dried and washed buffer; and creating a chemical etching on the sample.Type: GrantFiled: August 29, 2002Date of Patent: December 29, 2009Assignee: Centre National de la Recherche Scientifique - CNRSInventors: Azzedine Bousseksou, Christophe Vieu, Jean-Francois Letard, Philippe Demont, Jean-Pierre Tuchagues, Laurent Malaquin, Jerôme Menegotto, Lionel Salmon
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Patent number: 7639524Abstract: A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.Type: GrantFiled: January 20, 2006Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hun Kang, Jeong-Hee Han, Wan-Jun Park, Won-Joo Kim, Jae-Woong Hyun
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Publication number: 20090305432Abstract: A polypeptide can conduct electricity in a closed circuit. Conformational changes in the polypeptide due to posttranslational modifications or ligand binding can effect the conductive properties of the polypeptide which can be measured. In such a closed circuit, a polypeptide having at least one residue capable of reversible modification can be used as a molecular switch. Circuits comprising such molecular switches can be used, for example, in methods for assessing the modification state of a polypeptide, determining the activity of an enzyme of interest, identifying compounds that affect the activity of an enzyme of interest, storing data, detecting the presence of a compound and identifying inhibitors of protein-protein interactions.Type: ApplicationFiled: October 16, 2006Publication date: December 10, 2009Inventors: Lance Liotta, Emanuel Petricoin, David Geho
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Patent number: 7630227Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assembling one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.Type: GrantFiled: January 5, 2009Date of Patent: December 8, 2009Inventor: Bao Tran
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Patent number: 7612369Abstract: A memory device includes a semiconducting polymer film, which includes an organic dopant. The semiconducting polymer film has a first side and a second side. The memory device also includes a first plurality of electrical conductors substantially parallel to each other coupled to the first side of the semiconducting polymer layer, and a second plurality of electrical conductors substantially parallel to each other, coupled to the second side of the semiconducting polymer layer. The first and second pluralities of electrical conductors are substantially mutually orthogonal to each other. Further, an electrical charge is localized on the organic dopant.Type: GrantFiled: September 9, 2005Date of Patent: November 3, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventor: James Stasiak
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Publication number: 20090268511Abstract: Bacteriorhodopsin protein variants and methods using the bacteriorhodopsin variants for performance in holographic and three-dimensional (3D) memory storage devices are described. The amino acid and chemical modifications of bacteriorhodopsin provided herein achieve greatly enhanced protein performance. The memory storage devices write, read and erase data proficiently. The bacteriorhodopsin protein variants are useful in optical memory storage and associative processor systems. Irradiation of the light-sensitive protein with light of known wavelength causes the protein to switch between different states. The variants enter the branched photocycle via a single or a two photon process and form the permanent ‘Q’ state more efficiently than the wild-type bacteriorhodopsin protein. This branching photocycle of the variants is exploited in the fabrication of 3D memory storage devices.Type: ApplicationFiled: January 14, 2009Publication date: October 29, 2009Applicant: University of ConnecticutInventors: Robert R. Birge, Rekha Rangarajan, Kristina Nicole McCleary
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Patent number: 7606059Abstract: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged and formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state based on the polarity of voltage application in a non-volatile manner. The access element has a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on the semiconductor substrate and underlying the cell array for data reading and data writing in communication with the cell array.Type: GrantFiled: March 18, 2003Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 7605408Abstract: The present invention relates to reconfigurable circuitry, and more particularly to the reconfiguration of the characteristics of materials used in the formation of electronic circuitry as the result of applied external influences. Exemplary embodiments of the present invention provide an apparatuses, methods, electronic devices and computer program products that include a nanoscale material layer, and a programmable element in close proximity to at least a first section of the nanoscale material layer. The programmable element is configured to produce interference with an electron wave in at least the first section of the nanoscale material layer.Type: GrantFiled: April 25, 2008Date of Patent: October 20, 2009Assignee: Nokia CorporationInventors: Asta Karkkainen, Leo Karkkainen
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Patent number: 7599213Abstract: An apparatus includes a storage media having a surface coated with a lubricant, and a plurality of probes having tips contacting the lubricant, wherein the probes are coated with one of a fluorocarbon, perfluoropolyether, polytetrafluoroethylene, fluorinated ethylene propylene, polyethylene, or a hydrocarbon polymer.Type: GrantFiled: May 1, 2006Date of Patent: October 6, 2009Assignee: Seagate Technology LLCInventors: Paul Max Jones, Earl Chrzaszcz Johns, James Dillon Kiely, Lei Li, Yiao-Tee Hsia
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Patent number: 7593251Abstract: The memory cell comprises a field effect memory transistor comprising a nanowire covered by a type of memory molecules and an access transistor of the same type. A source of the access transistor is connected to a drain of the memory transistor. The nanowire of the access transistor and the nanowire of the memory transistor can be formed by a single nanowire having two ends respectively forming a drain of the access transistor and a source of the memory transistor. The memory device comprises a plurality of memory cells, an access transistor gate being connected to a word line and a memory transistor gate being connected to a write line.Type: GrantFiled: May 15, 2007Date of Patent: September 22, 2009Assignee: Commissariat a l'Energie AtomiqueInventor: Antoine Jalabert
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Publication number: 20090231906Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.Type: ApplicationFiled: May 21, 2009Publication date: September 17, 2009Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: Darrell Rinerson, Christophe Chevallier, Wayne Kinney, Edmond Ward
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Publication number: 20090225582Abstract: A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element.Type: ApplicationFiled: March 7, 2008Publication date: September 10, 2009Applicant: UNITY SEMICONDUCTOR CORPORATIONInventor: Lawrence Schloss
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Publication number: 20090225585Abstract: The invention encompasses self-contained charge storage molecules for use in memory devices such as for example static, permanent and dynamic random access memory. In particular, the invention encompasses molecules possessing structural features, which allow such molecules to form self-contained charge storage units for use, for example, in a molecular capacitor. The invention further encompasses operational systems comprising such self-contained charge storage molecules.Type: ApplicationFiled: December 24, 2008Publication date: September 10, 2009Inventor: J. Adrian Hawkins
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Patent number: 7583526Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.Type: GrantFiled: July 17, 2007Date of Patent: September 1, 2009Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
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Patent number: 7577078Abstract: A magnetic recording medium and an apparatus and a method for reading data using spin-dependent scattering of electrons are provided. The apparatus includes a probe, a magnetic recording medium, a control unit, and a measurement unit. The probe emits hot electrons through a Schottky junction or tunnel barrier. The magnetic recording medium includes a substrate, a first magnetic layer placed over the substrate, a non-magnetic layer placed over the first magnetic layer, and a second magnetic layer placed over the non-magnetic layer and having a magnetization direction parallel or anti-parallel with a magnetization direction of the first magnetic layer. The control unit applies voltage to the probe so that the probe can emit hot electrons. The measurement unit reads data recorded on the magnetic recording medium by detecting output current at the substrate that varies according to the parallel or anti-parallel alignment of magnetizations of the first and second magnetic layers.Type: GrantFiled: June 9, 2003Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Sung-dong Kim
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Publication number: 20090196090Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.Type: ApplicationFiled: December 10, 2008Publication date: August 6, 2009Inventors: Gregory S. Snider, Phillip J. Kuekes
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Patent number: 7564708Abstract: In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across the electrodes in one direction, and may be programmed in the electronic charge carrier mode by applying electrical potential across electrodes in the opposite direction.Type: GrantFiled: December 5, 2006Date of Patent: July 21, 2009Assignee: Spansion LLCInventors: Tzu-Ning Fang, Michael VanBuskirk, Swaroop Kaza
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Patent number: 7558101Abstract: Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli.Type: GrantFiled: December 14, 2007Date of Patent: July 7, 2009Assignee: Spansion LLCInventors: Hagop Nazarian, Michael Achter
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Patent number: 7558103Abstract: A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization free section in such a manner that a current is made to flow between the magnetization free section and the magnetization fixed section, a movable conductive tube having a fixed end and a free end, and a third electrode connected to the fixed end of the conductive tube. A switching operation is performed in such a manner that a spatial position of the conductive tube is caused to change depending on the magnetization direction of the magnetization free section.Type: GrantFiled: March 30, 2007Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Shiho Nakamura, Yuichi Motoi, Shigeru Haneda, Hirofumi Morise, Takahiro Hirai
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Patent number: 7554111Abstract: A bistable electrical device employing a bistable polymer body made from an electrically insulating polymer material in which doped nanofibers are dispersed. The doped nanofibers are composed of an electrically conductive nanofiber material and electrically conductive nanoparticles. The doped nanofibers impart bistable electrical characteristics to the polymer body, such that the polymer body is reversibly convertible between a low resistance state and a high resistance state by application of an electrical voltage.Type: GrantFiled: May 18, 2005Date of Patent: June 30, 2009Assignee: The Regents of the University of CaliforniaInventors: Yang Yang, Richard Kaner
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Publication number: 20090164435Abstract: A system for performing multi-dimensional quantum search, quantum computation, quantum memory, quantum storage, and quantum retrieval includes a structure and method for: enabling components and systems for quantum search, and more particularly to improved local and remote quantum computing and search components and systems; quantum memory component and systems; quantum storage components and systems; quantum retrieval components and systems; quantum logic gates; classical (non-quantum) search components and systems; integrated quantum-classical search components and systems; and integrated quantum-classical cryptosystems.Type: ApplicationFiled: December 17, 2008Publication date: June 25, 2009Inventor: Thomas J. Routt
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Patent number: 7550761Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: December 26, 2006Date of Patent: June 23, 2009Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Publication number: 20090154223Abstract: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.Type: ApplicationFiled: January 16, 2009Publication date: June 18, 2009Applicant: STMicroelectronics S.r.l.Inventors: Danilo Mascolo, Gianfranco Cerofolini
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Patent number: 7542334Abstract: A nanotube-based switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior.Type: GrantFiled: January 9, 2008Date of Patent: June 2, 2009Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
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Patent number: 7535778Abstract: The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a carbon nanotube memory, an atomic memory, a single electron memory, or a memory fabricated by a chemical bottom-up method, etc.Type: GrantFiled: March 2, 2006Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sik Yoon, In-Seok Yeo
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Publication number: 20090116277Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assembling one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.Type: ApplicationFiled: January 5, 2009Publication date: May 7, 2009Inventor: Bao Tran
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Patent number: 7525833Abstract: One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.Type: GrantFiled: October 21, 2005Date of Patent: April 28, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gregory S. Snider, Philip J. Kuekes
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Patent number: 7518905Abstract: This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory density (e.g., 1015 bits/cm3), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices are intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.Type: GrantFiled: November 2, 2005Date of Patent: April 14, 2009Assignees: The Regents of the University of California, North Carolina State UniversityInventors: David F Bocian, Werner G Kuhr, Jonathan Lindsey, Peter Christian Clausen, Daniel Tomasz Gryko
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Publication number: 20090091352Abstract: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior.Type: ApplicationFiled: October 6, 2008Publication date: April 9, 2009Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
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Patent number: 7515490Abstract: An organic memory at least includes a number of select lines, a number of data lines, a bit cell array, and a number of digital sensing circuits. The bit cell array includes a number of bit cells, wherein each bit cell includes an organic memory cell and a switch element. Each digital sensing circuit includes a current-to-voltage converter and a sensing block circuit. Therefore, a complete digital sensing mechanism of an organic memory IC is formed and is practicable and suitable for mass-production.Type: GrantFiled: June 12, 2006Date of Patent: April 7, 2009Assignee: Industrial Technology Research InstituteInventors: Jan-Ruei Lin, Shyh-Shyuan Sheu, Wei-Jen Chang
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Patent number: 7508039Abstract: Carbon nanotube (CNT) based devices include an actuator/switch that includes one or more fixed CNTs and a moveable CNT that can be urged toward or into contact with a selected fixed CNT with a magnetic field produced by a current in a control conductor. The control conductor can be formed of one or more CNTs, and the fixed and moveable CNTs can be retained by a support, and motion of the moveable CNT limited by a cavity defined in the support. In other examples, CNT FETS are used to form CNT transmission gates that are arranged to define circuits configured as multiplexers or to realize logical functions, addition, multiplication, or other operations such as Galois field arithmetic.Type: GrantFiled: May 4, 2005Date of Patent: March 24, 2009Assignee: State of Oregon Acting By and Through The State Board of Higher Education On Behalf of Portland State UniversityInventor: Anas N. Al-Rabadi
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Patent number: 7508707Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.Type: GrantFiled: December 31, 2007Date of Patent: March 24, 2009Assignee: Elpida Memory, Inc.Inventors: Kiyoshi Nakai, Kazuhiko Kajigaya, Isamu Asano
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Publication number: 20090059654Abstract: A novel magnetic memory cell utilizing nanotubes as conducting leads is disclosed. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry.Type: ApplicationFiled: September 1, 2008Publication date: March 5, 2009Inventor: Krishnakumar Mani
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Patent number: 7499309Abstract: A metal sulfide based non-volatile memory device is provided herein. The device is comprised of a substrate, a backplane, a planar memory media including a dense array of metal sulfide based memory cells, and a MEMS probe based actuator. The cells of the memory device are operative to be of two or more states corresponding to various levels of impedance. The MEMS actuator is operable to position micro/nano probes over the appropriate cells to enable reading, writing, and erasing the memory cells by applying a bias voltage.Type: GrantFiled: April 2, 2004Date of Patent: March 3, 2009Assignee: Spansion LLCInventors: Colin Bill, Michael A. VanBuskirk, Tzu-Ning Fang
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Patent number: 7499316Abstract: A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.Type: GrantFiled: March 19, 2007Date of Patent: March 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Gil Choi, Du-Eung Kim, Yu-Hwan Ro, Joon-Yong Choi, Beak-Hyung Cho, Woo-Yeong Cho
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Publication number: 20090052246Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: ApplicationFiled: June 30, 2008Publication date: February 26, 2009Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Frank GUO, Thomas RUECKES, Steven L. KONSEK, Mitchell MEINHOLD, Max STRASBURG, Ramesh SIVARAJAN, X. M. HUANG