Abstract: A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and configurable switches between the key nanowires and the value nanowires. The combination further includes a key microwire-nanowire grid (key MNG) electrically connected to the spaced-apart key nanowires, and a value microwire-nanowire grid (value MNG) electrically connected to the spaced-apart value nanowires. A key or value MNGs selects multiple nanowires for a given key or value.

Abstract: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.

Abstract: A memory device includes an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode; a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and a plurality of bit lines each connecting the second signal electrodes of a column of memory cells.

Abstract: A semiconductor memory device comprises a plurality of memory cells each capable of storing at least three different states; a first sense amplifier for amplifying a ternary potential read out in accordance with a state stored in a selected memory cell based on a comparison with a first reference potential; and a second sense amplifier for amplifying a ternary potential read out in accordance with a state stored in the selected memory cell based on a comparison with a second reference potential. In the semiconductor memory device, the ternary potential comprises a high potential, a medium potential and a low potential, the first reference potential is set between the low potential and the medium potential, and the second reference potential is set between the high potential and the medium potential.

Abstract: A memory element which has high affinity with a conventional semiconductor process, which has a switching function of completely interrupting electric conduction paths by in a mechanical manner, and in which nonvolatile information recording is enabled is realized. An electromechanical memory which is formed on a substrate, which is formed by interposing a memory cell by electrodes, and which has a movable electrode that is a beam stretched in the air via a post portion is realized. According to the configuration, a nonvolatile memory can be realized by a simple structure, and it is possible to realize a high-performance electromechanical memory which is conventionally difficult to be realized, and in which the power consumption is low and the cost is low, and an electric apparatus using it.

Abstract: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.

Abstract: An analog memory may be formed using a phase change material. The phase change material may assume one of a number of resistance states which defines a specific analog characteristic to be stored.

Abstract: Various embodiments of the present invention are directed to electronic means for reading the content of a nanowire-crossbar memory. In one embodiment of the present invention, a microscale or sub-microscale signal line is interconnected with one set of parallel nanowires emanating from a nanowire-crossbar memory by configurable, nanowire-junction switches. The microscale or sub-microscale signal line serves as a single-wire multiplexer, allowing the contents of any particular single-bit storage element within the nanowire-crossbar memory to be read in a three-cycle READ operation.

Abstract: A memory device includes an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode; a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and a plurality of bit lines each connecting the second signal electrodes of a column of memory cells.

Abstract: A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

Abstract: Each memory cell of a molecular battery memory device includes a combination of a molecular battery and a selection transistor, and a parasitic capacitance is present in the molecular battery. A PN junction is present in the selection transistor, and is inversely biased. Therefore, a junction leak current flows. Accordingly, a charge accumulated in the parasitic capacitance is gradually discharged by a junction leak of the selection transistor, and a final potential of a node decreases toward a substrate potential Vs of the transistor. However, a difference between a substrate potential Vs and a reference potential Vp (=Vs?Vp) is set substantially equal to an open-circuit voltage of the molecular battery. Because the potential of the node converges to the open-circuit voltage without exception from the viewpoint of a plate wiring, an S/N ratio at the data reading time can be increased.

Abstract: Using a synthetic molecular spring device in a system for dynamically controlling a system property, such as momentum, topography, and electronic behavior. System features (a) the synthetic molecular spring device having (i) at least one synthetic molecular assembly each featuring at least one chemical unit including at least one: (1) atom; (2) complexing group complexed to at least one atom; (3) axial ligand reversibly physicochemically paired with at least one complexed atom; and (4) substantially elastic molecular linker; and, (ii) an activating mechanism directed to at least one atom-axial ligand pair; and, (b) a selected unit operatively coupled to synthetic molecular assembly, and exhibiting the system property.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.

Abstract: A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Abstract: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior.

Abstract: A functional molecular element whose functions can be controlled by an electric field based on a new principle. A Lewis base molecule (14) with positive permittivity anisotropy or a dipole moment in the major axis direction of the molecule is disposed, via a metal ion (3) that can act as a Lewis acid, in a pendant-like form on a key molecule (2) in the form of a line or film that has a conjugated system and exhibits conductivity, thereby forming a functional molecular element 1 that can realize a function where the conformation changes due to the application of an electric field. The conductive key molecule (2) and the Lewis base molecule (14) form a complex with the metal ion (3). When an electric field is applied in a direction perpendicular to the plane of the paper in FIG. 1(b), for example, the Lewis base molecule (14) performs a 90° “neck twisting” movement with the up-down direction in the drawing as the axis.

Abstract: Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.

Abstract: A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact probes in accordance with the present invention can be applied to a phase change media, for example, to form an indicia in the phase change media by changing the electrical resistivity of a portion of the phase change media.

Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract: Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

Abstract: A nanomechanical device includes a nanostructure, such as a MWNT, located between two electrodes. The device switches from an OFF state to an ON state by extension of at least one inner shell of the nanostructure relative to at least one outer shell of the nanostructure upon an application of a voltage between the electrodes. If desired, the device may also switch from the ON state to the OFF state upon an application of a gate voltage to a gate electrode located adjacent to the nanostructure.

Abstract: The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.

Abstract: Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read if a charge is stored in the charge containment layer, a charge is formed on the beam. If a charge is stored then forces between the charged beam and the charge containment layer will displace the free-moving portion of the beam. This movement may be sensed by a sense contact. Alternatively, the beam may contact a sense contact at an ambient frequency when no charge is stored. Changing the amount of charge stored may change this contact rate. The contract rate may be sensed to determine the amount of stored charge.

Abstract: A nano tube cell and a memory device using the same features a cross point cell using a capacitor and a PNPN nano tube switch to reduce the whole memory size. In the memory device, the unit nano tube cell comprising a capacitor and a PNPN nano tube switch which does not an additional gate control signal is located where a word line and a bit line are crossed, so that a cross point cell array is embodied. As a result, the whole chip size is reduced, and read and write operations are effectively improved.

Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Methods of sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract: A memory device includes a mechanical element that exhibits distinct bistable states under amplitude modulation. The states are dynamically bistable or multi-stable with the application of a drive signal of a given frequency. The natural resonance of the element in conjunction with a hysteretic effect produces distinct states over a specific frequency range. Devices with multiple elements that respond to different frequency ranges provided on a common contact are formed with improved density. The devices may be excited and read with magnetomotive, capacitive, piezoelectric and/or optical methods. The devices may be planar oriented or out of plane oriented to permit three dimensional memory structures. DC biases may be used to shift frequency responses to permit an alternate method for differentiating states of the element.

Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

Abstract: A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage location within the volume of phase change material.

Abstract: A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Abstract: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

Abstract: A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube switch which does not require an additional gate control signal is located between a word line and the sub-bit line, so that a cross point cell array is embodied to reduce the whole chip size.

Abstract: A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact probes in accordance with the present invention can be applied to a phase change media, for example, to form an indicia in the phase change media by changing the electrical resistivity of a portion of the phase change media.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.

Abstract: A data storage device assembly includes a data storage device having two sidewalls, each sidewall having a first positioning post; a supporting bracket having two sidewalls, one of the sidewalls defining a guiding slot for locating the first positioning post; a driving member movably attached to the supporting bracket, the driving member having a sliding post; a pivoting member pivotally located between the driving member and the supporting bracket, the pivoting member defining a sliding slot for the sliding post to slide therein, and having a stopping block for locating the first positioning post; and a first elastic component for urging the driving member to move towards an original position. When the driving member is pushed, the sliding post of the driving member slides in the sliding slot to urge the pivoting member to rotate, thereby causing the first positioning post to disengage from the stopping block.

Abstract: The memory cell comprises a field effect memory transistor comprising a nanowire covered by a type of memory molecules and an access transistor of the same type. A source of the access transistor is connected to a drain of the memory transistor. The nanowire of the access transistor and the nanowire of the memory transistor can be formed by a single nanowire having two ends respectively forming a drain of the access transistor and a source of the memory transistor. The memory device comprises a plurality of memory cells, an access transistor gate being connected to a word line and a memory transistor gate being connected to a write line.

Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.

Abstract: An embodiment of a probe storage device in accordance with the present invention can include an electrostatic actuator for controlling the z-position of a cantilever having a contact probe tip extending therefrom. The electrostatic actuator can comprise two electrodes: the cantilever and a conductive portion in overlapping proximity to the cantilever. By controlling the z-position of the cantilever, the contact probe tip can be selectively engaged and disengaged from a surface of a memory media, thereby allowing the contact probe to selectively read from and/or write to the memory media.

Abstract: A molecular memory element comprising a switching device; at least a first bit line and a first word line coupled to said switching device; and an array of storage locations, each coupled to a bit line and a word line, said elements comprising a first electrode with storage molecules comprising redox active molecules, and said array comprising a second electrode.

Abstract: An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.

Abstract: The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling a volume of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a capacitor, and a PNPN nano tube cell having a PNPN diode switch selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: Systems and methodologies are provided for adjusting threshold associated with a polymer memory cell's operation by applying thereupon a regulated electric field and/or voltage pulse width, during a post fabrication stage. Such customization of programming thresholds can typically be obtained at any cycle of programming the memory cell, to increase flexibility in circuit design. Accordingly, the present invention supplies both a current-voltage domain, and/or a frequency-time domain, to facilitate adjusting the program thresholds of the polymer memory cell.

Abstract: In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: An improved high-density digital storage device uses placement of mobile ions within a memory layer to record digital data. In an embodiment of the invention, the mobile ions comprise sodium ions or other alkali metal ions implanted in a silicon oxide memory layer. In a further embodiment of the invention, a scanning nanotip array is used to position the mobile ions via an electric field as well as to read the positions of the mobile ions. In a further embodiment of the invention, a grid-addressable array of transistors is used to provide scanning tips.

Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.