Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of first and second word lines respectively connected to the memory cells, a plurality of first drivers for driving the first word lines selected during a read operation, and a plurality of second drivers for driving the second word lines selected during a write operation, the second driver having a different drive capability from the first driver's.

Abstract: A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages.

Abstract: To improve reliability of a semiconductor device having an SRAM. The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in this order when viewed in a row direction. First and second positive-phase access transistors are disposed in the first p well, first and second driver transistors are disposed in the second p well, and first and second negative-phase access transistors are arranged in the third p well.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

Abstract: A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.

Abstract: Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.

Abstract: A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.

Abstract: It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines.

Abstract: An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

Abstract: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation.

Abstract: A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer.

Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has : a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has : replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A static random access memory (SRAM) includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar.

Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2) configured with the four pull-down devices to form two cross-coupled inverters, wherein two of the pass-gate devices are configured to form a first port and another two of the pass-gate devices are configured to form a second port.

Abstract: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Abstract: A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.

Abstract: An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.

Abstract: A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored.

Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

Abstract: A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of the magnetic tunnel junction to a first selection transistor; wherein the cell further comprises a second strap portion extending opposite to the first strap portion and connecting laterally said one end of the magnetic tunnel junction to a second selection transistor, and in that said first and second strap portions being adapted for passing a portion of current via the first and second selection transistors. The disclosed cell has lower power consumption than conventional MRAM cells.

Abstract: Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Abstract: The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.

Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.

Abstract: One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other.

Abstract: A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns. The plurality of processing circuits may each be configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of the plurality of columns to determine a match. The compare may occur on a first clock cycle of an input clock signal. Each of the plurality of processing circuits may be configured to power down a respective column of the memory array if the test bit of the input data word does not match the test bit of the column.

Abstract: One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

Abstract: A solid-state memory in which stability assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an isolation gate connected between one of the storage nodes and the input of the opposite inverter. The isolation gate may be realized by complementary MOS transistors connected in parallel, and receiving complementary isolation control signals. In read cycles, or in unselected columns during write cycles, the isolation gate is turned off slightly before the word line is energized, and turned on at or after the word line is de-energized. By isolating the input of one inverted from the opposite storage node, the feedback loop of the cross-coupled inverters is broken, reducing the likelihood of a cell stability failure.

Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.

Abstract: A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract: An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.

Abstract: In a multipart SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

Abstract: A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.

Abstract: An SRAM bitcell architecture is described having a dedicated read port (N0/N1/N6, N3/N4/N7) with pull up transistors (N6, N7) that shares at least a first bit line pair (23, 24) and word line signal (25), thereby providing separate data access read paths to a 6T SRAM architecture such that the read port is connected to drive the cell read node without exposing the memory cell during read operations and to act as a write port during write operations.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.