Abstract: A sensor includes a structure body including a deforming portion, and a first sensing element provided at the deforming portion. The first sensing element includes first to fourth magnetic layers and a first intermediate layer. The first magnetic layer is provided between the second and third magnetic layers. The fourth magnetic layer is provided between the first and third magnetic layers. The first intermediate layer is provided between the second and first magnetic layers. The third magnetic layer includes at least one of a first material or a second material. The first material includes at least one selected from the group consisting of Ir—Mn, Pt—Mn, Pd—Pt—Mn, and Ru—Rh—Mn. The second material includes at least one of CoPt, (CoxPt100-x)100-yCry, or FePt. A crystallinity of at least a portion of the fourth magnetic layer is higher than a crystallinity of the first magnetic layer.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: According to one embodiment, a magnetic memory device includes a first conductive layer, a first stacked body, and a controller. The first conductive layer includes a first region, a second region, and a third region between the first region and the second region. The first stacked body includes a first magnetic layer, a second magnetic layer provided between the third region and the first magnetic layer in a first direction crossing a second direction, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second direction is from the first region toward the second region. The controller electrically is connected to the first region, the second region, and the first magnetic layer. The controller performs at least first to third operations. In the operations, the controller sets the first stacked body to first to third resistance state.

Abstract: A magnetic storage device includes a first and a second stacked body including a first ferromagnetic body and a second ferromagnetic body, respectively. A first magnetoresistive effect element includes the first ferromagnetic body and a third ferromagnetic body with a first nonmagnetic body between the first and third ferromagnetic bodies. A second magnetoresistive effect element includes the first ferromagnetic body and a fourth ferromagnetic body with a second nonmagnetic body between the first and fourth ferromagnetic bodies. A third magnetoresistive effect element includes the second ferromagnetic body and a fifth ferromagnetic body with a third nonmagnetic body between the second and fifth ferromagnetic bodies. A fourth magnetoresistive effect element includes the second ferromagnetic body and a sixth ferromagnetic body with a fourth nonmagnetic body between the second and sixth ferromagnetic bodies. The third and fourth ferromagnetic bodies are between the first and second stacked bodies.

Abstract: A nonvolatile storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a memory cell between the first and second wirings, a reading circuit configured to read data from the memory cell during a first and a second reading period, a writing circuit configured to write reference data into the memory cell during a writing period between the first and second reading periods, and a determination circuit configured to compare a first voltage which is based on the data read during the first reading period with a second voltage which is based on the data read during the second reading period, to determine the value of the data read during the first reading period. A current is caused to flow in the memory cell during the first reading period, the writing period, and the second reading period.

Abstract: The present invention relates to a semiconductor device. The semiconductor device based on the spin orbit torque (SOT) effect, according to an example of the present invention, comprises the first electrode; and the first cell and the second cell connected to the first electrode, wherein the first and the second cells are arranged on the first electrode separately; the magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; the magnetization direction of the free magnetic layer is changed when the current applied on the first electrode exceeds critical current value of each cell; and the critical current value of the first cell is different from that of the second cell.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: Disclosed are systems and methods for improving the performance of magnetoresistive random access memory (MRAM). MRAM is one of the promising potential replacements for existing DRAM and SRAM memory devices due to the many advantages of the technology which include non-volatility, fast read and write speeds, improved read and write endurance, and low operating voltage. In one embodiment, the processing rates or other activity of circuits nearby an MRAM cell subject to write operations can be increased to increase the temperature of the MRAM cell. The increased temperature lowers the write field required during a write operation, which in turn lowers the power requirement and the switching time of the MRAM cell.

Abstract: Provided is a spin current magnetization rotational element including: a first ferromagnetic metal layer for a magnetization direction to be changed; and a spin-orbit torque wiring. The spin-orbit torque wiring has a structure in which a spin conduction layer and an interfacial spin generation layer are alternately laminated in the first direction, the number of a plurality of the interfacial spin generation layers is two or greater, and in the spin-orbit torque wiring, one of the plurality of interfacial spin generation layers is closest to the first ferromagnetic metal layer.

Abstract: A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.

Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.

Abstract: Devices or circuits based on spin torque transfer (STT) and Spin Hall effect are disclosed by using a spin Hall effect (SHE) metal layer coupled to a magnetic free layer for various applications. The efficiency or strength of the STT effect based on this combination of SHE and STT can be enhanced by an interface modification between the SHE metal layer and the magnetic free layer or by modifying or engineering the SHE metal layer by doping the SHE metal with certain impurities or other means.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

Abstract: A magnetic memory device that includes magnetic read elements and magnetic reference cells. The magnetic reference cells include magnetic tunnel junction elements having the same construction as the magnetic read elements. The reference cells produce a reference signal that can be compared with a read signal from the magnetic read element to determine whether the read element is in a high or low resistance state. During creation of the reference signal, the current passes in such a way so that reference cells are forced to be in the right state while causing no disturbance to the reference cell. The reference cell includes magnetic tunnel junction elements and also includes circuitry configured to produce a magnetic field that biases the magnetic tunnel junction elements of the reference cell into a desired magnetic state to ensure that the desired magnetic state of the reference cell magnetic tunnel junction elements is maintained.

Abstract: A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.

Abstract: Provided are a magnetic tunnel junction device and a magnetic resistance memory device which are capable of both reducing a write current and increasing a write speed. The magnetic tunnel junction device includes a free layer having a first magnetization direction that is changeable, a pinned layer that is configured to maintain a second magnetization direction in a predetermined direction, and an insulating layer between the free layer and the pinned layer. The free layer includes a first free layer having perpendicular magnetic anisotropy and high polarizability, and a second free layer that is antiferromagnetic-coupled to the first free layer.

Abstract: Provided is a spin current magnetization rotational element including: a spin-orbit torque wiring that extends in a first direction and is configured to generate a spin current; a first ferromagnetic layer that is laminated in a second direction intersecting the spin-orbit torque wiring and is configured for magnetization direction to be changed; and a first perpendicular magnetic field applying layer that is disposed to be separated from the spin-orbit torque wiring and the first ferromagnetic layer, the first perpendicular magnetic field applying layer being configured to apply an assistant magnetic field assisting a magnetization rotation of the first ferromagnetic layer.

Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array.

Abstract: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Abstract: An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

Abstract: A semiconductor device includes a device magnetic tunnel junction (MTJ) and sensor MTJs. A spin polarization of a free layer of the device MTJ is configurable based at least in part on electrical energy supplied to the device MTJ. A spin polarization of a corresponding free layer of each sensor MTJ is configurable based at least in part on a magnetic field created by the spin polarization of the free layer of the device MTJ. A circuit disposed is in electrical communication with the plurality of sensor MTJs and configured to determine the corresponding free layer spin polarizations of each of the sensor MTJs based at least in part on electrical energy supplied to the sensor MTJs by the circuit. The circuit is configured to determine a magnetoresistance of the device MTJ based at least in part on the determined corresponding free layer spin polarizations of the sensor MTJ.

Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Abstract: A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

Abstract: Simple device replacement (SDR), low-cost class A compatible devices that store and use configuration tables for use in performing a node replacement may be used. The use of SDR using 802.3 Ethernet-enabled class A devices allows for dispensing with an external management computer or device-mounted additional hardware (e.g., push-button, SD card, etc.), and for performing node replacement while the network remains operating. A modified token ring or logical ring configuration and process may also be utilized. In an embodiment, a logical ring with a token, which may be used as a distributed scheduler that is circulated amongst network nodes, may be provided. The use of a modified token ring may provide for managing low-priority traffic on an 802.3 network for sensors to utilize low-priority communications without impacting high-priority communications.

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

Abstract: The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.

Abstract: A semiconductor storage device includes first lines second lines, and memory cells. The detection circuit detects data stored in the memory cells. A first transistor is electrically connected to the second lines between the memory cells and the detection circuit. A controller brings the first transistor to an intermediate state between an on-state and an off-state and thereafter brings the first transistor to the on-state to transmit a voltage of the second line to the detection circuit, in a data read operation, while a read voltage is applied to a first memory cell among the memory cells, the first memory cell being connected to a selected first line selectively driven from among the first lines and connected to a selected second line selectively driven from among the second lines, and the first transistor connected to the selected second line.

Abstract: A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.

Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.

Abstract: A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

Abstract: Spintronic devices based on metallic antiferromagnets having a non-collinear spin structure are provided. Also provided are methods for operating the devices. The spintronic devices are based on a bilayer structure that includes a spin torque layer of an antiferromagnetic material having a non-collinear triangular spin structure adjoining a layer of ferromagnetic material.

Abstract: A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.

Abstract: A spin-orbit torque type magnetization reversal element including a ferromagnetic metal layer with a varying magnetization direction; and spin-orbit torque wiring that extends in a first direction intersecting with a stacking direction of the ferromagnetic metal layer and that is joined to the ferromagnetic metal layer; wherein when viewed from the first direction, the spin-orbit torque wiring is asymmetrical in a second direction that is orthogonal to the first direction and the stacking direction, with respect to an axis that passes through a center, in the second direction, of the ferromagnetic metal layer.

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

Abstract: Neuron circuit structures are presented which employ magnetic tunnel junction (MTJ) elements that change state probabilistically in response to application of electrical source currents that emulate synaptic activity. Some implementations form probabilistic neuron circuits using homogeneous perpendicular spin-transfer torque (STT) MTJ elements. These neuron circuits include a perpendicular STT reference MTJ element coupled via an electrical node with a perpendicular STT neuron MTJ element that can change state. The electrical node for each neuron circuit couples a neuron MTJ element or “perturbation” element to a reference element, and also to an electrical current employed to influence probabilistic magnetization state changes in the perturbation MTJ element. A read current can be applied to the perturbation element to produce an output voltage at the electrical node indicative of a magnetization state of the perturbation element.

Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.

Abstract: In example embodiments, a SOT magnetic memory and operation method are provided that utilize SOT driven domain wall motion to achieve subsequent switching without the need for an external assist magnetic field. The magnetic memory includes a magnetic tunnel junction having a reference layer, a tunnel barrier layer and a free layer, where the tunnel barrier layer is positioned between the reference layer and free layer. A spin-orbit torque layer is disposed adjacent to the free layer. A pair of pinning site are positioned at a longitudinal end of the free layer and each has an opposite magnetization direction from the other. The SOT layer is configured to exert SOT and switch a magnetization direction of the free layer via domain wall motion in a direction of current flow when an electric current is passed through a length of the SOT layer.

Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

Abstract: A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.

Abstract: A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

Abstract: A spin-orbit torque magnetization rotating element includes a spin-orbit torque wiring and a laminated body laminated on the spin-orbit torque wiring. The laminated body includes a first ferromagnetic layer independently having an axis of easy magnetization in a first direction, a nonmagnetic antiferromagnetic coupling layer, and a second ferromagnetic layer independently having an axis of easy magnetization in a second direction, in order from the side of the spin-orbit torque wiring, and the first direction crosses the second direction.

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.

Abstract: An example device for performing a write operation using a spintronic Hall effect includes a Spin Hall Effect (SHE) structure, a Magnetic Tunnel Junction (MTJ) element, and processing circuitry. The MTJ element includes a free structure, a pinned structure, and a tunnel barrier arranged between the free structure and the pinned structure. The free structure comprises a plurality of free layers. The free structure is arranged with the SHE structure such that current in the SHE structure induces spin transfer into the free structure. The processing circuitry is configured to receive an instruction to set the MTJ element to a target state of a plurality of states and in response to receiving the instruction, generate electrical current through the spin Hall effect structure to modify a resistance of the MTJ element to correspond to the target state.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit-torque wiring which extends in a first direction; and a first ferromagnetic layer which is laminated in a second direction intersecting the spin-orbit-torque wiring, wherein the spin-orbit-torque wiring includes a convex portion which protrudes in the second direction in relation to a first surface on the side of the first ferromagnetic layer at a connecting part between the spin-orbit-torque wiring and the first ferromagnetic layer.

Abstract: A magnetic tunnel junction element configured by stacking, in a following stack order, a fixed layer formed of a ferromagnetic body and in which a magnetization direction is fixed, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body and in which the magnetization direction is fixed, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed by sandwiching an insertion layer formed of a nonmagnetic body between first and second ferromagnetic layers, wherein the magnetic coupling layer is formed using a sputtering gas in which a value of a ratio in which a mass number of an element used in the magnetic coupling layer divided by the mass number of the sputtering gas itself is 2.2 or smaller.

Abstract: In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

Abstract: A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blref of the second subset of the reference memory bit cells outputs a read reference signal.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A bit cell driving mechanism is disclosed. The mechanism includes a bit cell which includes a first magnetic tunnel junction (MTJ) cell, including a pinned layer, a non-magnetic layer, a free layer having two magnetic regions separated by a laterally moveable domain wall, and a spin-hall metal layer configured to receive an electrical current therethrough which causes the DW to move laterally. The mechanism also includes a second MTJ cell coupled to the first MTJ cell as well as an interconnect driver configured to provide electrical current to the first MTJ cell during a write operation.

Abstract: A magnetic structure includes a magnetic tunnel junction based on a synthetic antiferromagnetic free layer which is regulated by an electric field, and a spin-orbit layer located below the magnetic tunnel junction. The transformation from the antiferromagnetic coupling to the ferromagnetic coupling of the free layer based on a synthetic antiferromagnetic multilayer structure is controlled by an electric field. A spin-orbit torque magnetic random access memory, which includes the magnetic structure, is able to realize stable data writing under the combined interaction of electric field and current, and has advantages of simple structure for scaling, ultralow power consumption, ultrahigh speed of switching, radiation resistance and non-volatility.