Amorphous (electrical) Patents (Class 365/163)
  • Patent number: 12201041
    Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-I Wu
  • Patent number: 12200933
    Abstract: A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: January 14, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Yu Lee, Teng-Hao Yeh
  • Patent number: 12198757
    Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 14, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 12192024
    Abstract: Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Bassam N. Coury, Sujoy Sen, Thomas E. Willis, Durgesh Srivastava
  • Patent number: 12182701
    Abstract: The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 31, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Po-Kai Hsu, Ming-Liang Wei
  • Patent number: 12176030
    Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: December 24, 2024
    Assignees: Universite D'Aix Marseille, Centre National de la Recherche, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Michel Portal, Vincenzo Della Marca, Jean-Pierre Walder, Julien Gasquez, Philippe Boivin
  • Patent number: 12156411
    Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Paolo Tessariol, Enrico Varesi, Lorenzo Fratin
  • Patent number: 12153823
    Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Davide Fugazza, Dany-Sebastien Ly-Gagnon, DerChang Kau
  • Patent number: 12154623
    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Noble Narku-Tetteh, Yasir Mohsin Husain, Ripudaman Singh, Nicolas L. Irizarry
  • Patent number: 12137621
    Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mauricio Manfrini, Chung-Te Lin, Gerben Doornbos, Marcus Johannes Henricus van Dal
  • Patent number: 12131793
    Abstract: Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Agostino Pirovano
  • Patent number: 12087361
    Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: September 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bilal Ahmad Janjua, Jongryul Kim, Venkataramana Gangasani, Jungyu Lee
  • Patent number: 12087360
    Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: September 10, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, WEEBIT NANO LTD
    Inventors: Gabriel Molas, Alessandro Bricalli, Guiseppe Piccolboni, Amir Regev
  • Patent number: 12073887
    Abstract: An operating method of a semiconductor device including a controller and a non-volatile memory device operating under control of the controller is provided. The operating method includes determining, by the controller, whether the non-volatile memory device satisfies a block program condition; based on the non-volatile memory device satisfying the block program condition, performing a block program operation a plurality of times; and based the non-volatile memory device not satisfying the block program condition, performing an erase operation.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: August 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanggyu Ko, Yeongmin Yoo
  • Patent number: 12069970
    Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 12068123
    Abstract: A switch device includes a phase change switch and a memory for storing a target state of the phase change switch. A controller determines a phase state of the phase change switch, and, if the state of the phase change switch does not correspond to the target state, controls a heater of the phase change switch to change the state of the phase changes switch to the target state.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: August 20, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans Taddiken, Dominik Heiss, Christoph Kadow
  • Patent number: 12057178
    Abstract: In some aspects, the techniques described herein relate to a circuit including: a memory cell; a source follower, a source terminal of the source follower communicatively coupled to the memory cell; a voltage source; an operational amplifier, a non-inverting input of the operational amplifier communicatively coupled to the voltage source; and a replica source follower, a gate of the replica source follower communicatively coupled to an output of the operational amplifier and a source terminal of the replica source follower communicatively coupled to an inverting input of the operational amplifier via a feedback loop.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kijun Nam, Mingdong Cui
  • Patent number: 12056601
    Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 6, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 12046282
    Abstract: The invention is notably directed to a device comprising a plurality of resistive memory elements. The plurality of resistive memory elements comprises a resistive material. The device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to perform a temporary resistance change of the resistive material of the subset for a predefined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that a resistance of the subset of the plurality of resistive elements reverts automatically during the predefined retention period from the second resistance state to the first resistance state by an inherent material property of the resistive material, thereby automatically deleting the second binary state.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: July 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ghazi Sarwat Syed, Abu Sebastian
  • Patent number: 12014050
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Ching-Huang Lu, Murong Lang
  • Patent number: 12014784
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nevil N. Gajera, Karthik Sarpatwari, Zhongyuan Lu
  • Patent number: 12014774
    Abstract: A method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Xinyu Bao
  • Patent number: 12004432
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: June 4, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Roberto Simola, Yohann Moustapha-Rabault
  • Patent number: 11984159
    Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 14, 2024
    Assignee: SK hynix inc.
    Inventors: Moo Hui Park, Seok Joon Kang, Jun Ho Cheon
  • Patent number: 11978513
    Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert J. Gleixner
  • Patent number: 11978511
    Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
  • Patent number: 11957069
    Abstract: An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Oleg Gluschenkov, Alexander Reznicek, Soon-Cheon Seo
  • Patent number: 11955173
    Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Chien-Min Lee, Xinyu Bao
  • Patent number: 11948638
    Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Andrea Martinelli, Maurizio Rizzi
  • Patent number: 11942183
    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
  • Patent number: 11942146
    Abstract: Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Win-San Khwa, Kerem Akarvardar, Yu-Sheng Chen
  • Patent number: 11915752
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Patent number: 11895851
    Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Lorenzo Fratin
  • Patent number: 11892928
    Abstract: Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 6, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Vinayak Bhat
  • Patent number: 11889773
    Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Injo Ok, Jin Ping Han, Timothy Mathew Philip, Matthew Joseph BrightSky, Nicole Saulnier
  • Patent number: 11887661
    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Mattia Robustelli, Alessandro Sebastiani
  • Patent number: 11877457
    Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Corrado Villa, Stefan Frederik Schippers, Efrem Bolandrina
  • Patent number: 11875847
    Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 16, 2024
    Assignees: Universite D'Aix Marseille, Centre National De La Recherche Scientifique, STMicroelectro (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Michel Portal, Vincenzo Della Marca, Jean-Pierre Walder, Julien Gasquez, Philippe Boivin
  • Patent number: 11862293
    Abstract: A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Noriyasu Kumazaki
  • Patent number: 11854615
    Abstract: Methods, a memory device, and a system are disclosed to reduce power consumption in a cross-point memory device, including providing a first portion of a first pulse of a memory operation to a memory cell at a first time using a first capacitive discharge from a first discharge path, and providing a second portion of the first pulse of the memory operation to the memory cell at a second time, later than the first time, using a second discharge path.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • Patent number: 11848049
    Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: December 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunheub Song, Yoonseong Choi
  • Patent number: 11849655
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Patent number: 11817171
    Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Nantero, Inc.
    Inventors: Takao Akaogi, Jia Luo, Nancy See Loiu Leong
  • Patent number: 11810617
    Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Hemant P. Rao, Shylesh Umapathy, Sanjay Rangan
  • Patent number: 11800816
    Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Mattia Robustelli
  • Patent number: 11769551
    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11765916
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara, Rieko Funatsuki, Yoshiki Kamata, Misako Morota, Yoshiaki Asao, Yukihiro Nomura
  • Patent number: 11763886
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • Patent number: 11756616
    Abstract: A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: September 12, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Nakao, Masayuki Hiromoto, Hisanao Akima, Teruo Ishihara, Takuji Yamamoto
  • Patent number: 11751379
    Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Kim, Kwang-Ho Park, Yong-Hoon Son, Hyunji Song, Gyeonghee Lee, Seungjae Jung