Abstract: The present provision includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices uses an electrical distance calculator to determine an electrical distance from a memory cell to a respective driver of the plurality of drivers. The memory device also uses a driver modulator to modulate the corresponding signal based at least in part on the electrical distance.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Abstract: There is provided a selection device that includes a first electrode, a second electrode opposed to the first electrode, a semiconductor layer provided between the first electrode and the second electrode, and including at least one kind of chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one kind of first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si), and a first heat bypass layer provided at least in a portion around the semiconductor layer between the first electrode and the second electrode and having higher thermal conductivity than the semiconductor layer.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

Abstract: A nonvolatile memory apparatus may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When the selected memory cell was snapped back, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to write data. When the selected memory cell is not snapped back, the write circuit may apply no voltage and no current to the selected memory cell. The sense amplifier may sense whether the selected memory cell was snapped back.

Abstract: Provided herein are a nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of word lines having a first word line and a plurality of memory cells connected to the first word line. The plurality of memory cells includes a plurality of monitoring cells and a plurality of data cells each data cell configured to store N-bit data, N being a natural number. The nonvolatile memory device is configured to perform a first program on the plurality of data cells and a detection program different from the first program on the one or more monitoring cells after performing the first program.

Abstract: A method of tuning a PCM device is disclosed. The method includes receiving a command and determining if the command is a SET command or a RESET command. When the command is a RESET command, the method provides a short pulse across a resistive electrode and a top electrode through a phase change material generating amorphous PCM at the point of highest voltage across the PCM region.

Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

Abstract: A reconfigurable phase change device with methods for operating and forming the same are disclosed. An example device can comprise a reconfigurable layer comprising a phase change material, and a set of contacts connected with the reconfigurable layer. The set of contacts can comprise at least a first contact, a second contact, and a third contact. The device can comprise at least one control element electrically coupled with one or more of the set of contacts. The at least one control element can be configured to supply a first control signal to one or more of the set of contacts. The first control signal can be configured to modify a first portion of the reconfigurable layer thereby isolating the first contact from the second contact and the third contact.

Abstract: A resistive memory device is provided. The resistive memory device includes a resistive memory cell electrically connected to a local word line node; a local word line transistor configured to electrically connect the local word line node to a global word line node; a global word line transistor configured to electrically connect the global word line node to a sensing node; and a margin compensation circuit comprising a margin compensation switch electrically connected to the local word line node and the global word line node.

Abstract: Multi-level cell (MLC) cross-point memory cells can store more than 1 bit per cell. In one example, MLC write operations for cross-point memory can be achieved by independently changing the state of the switch element and the memory element. The memory cell can be programmed to multiple states, such as a high threshold voltage state (where both the memory element and switch element exhibit a high threshold voltage or resistance), a low threshold voltage state (where both the memory element and select element exhibit a low threshold voltage or resistance), and one or more intermediate resistance states. In one example, additional resistance states can be programmed by setting the switch element and memory element to opposite states (e.g., one of the switch element and memory element is in a high resistance state and the other is in a low resistance state) or by placing both the switch element and memory element in different intermediate states.

Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n?1)-th stepped voltage level of the post-write pulse.

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract: The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component.

Abstract: A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.

Abstract: A nonvolatile memory device includes a command decoder that receives and decodes a first command and a second command, a first control circuit that generates first control information under control of the command decoder decoding the first command, a second control circuit that generates second control information under control of the command decoder decoding the second command, a first bank that includes a first memory cell which operates based on the first control information, and a second bank that includes a second memory cell which operates based on the second control information. A first time to output data from the first bank in response to the first command is different from a second time to output data from the second bank in response to the second command.

Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.

Abstract: A phase-change memory cell, including, in sequence in the following order: a first electrode layer, a switching layer comprising vanadium oxide (VOx) material, a phase-change material layer, and a second electrode layer, is provided. The switching layer is adapted to control the phase-change material layer to switch between a crystalline state and an amorphous state when a voltage is applied to the first electrode layer and the second electrode layer.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: Apparatuses and techniques are described for forming of selectors in a memory device such as a crosspoint memory array. A threshold switching selector is in series with a resistance-switching memory cell in a storage node. Prior to a first switching operation in the array, a stimulus is applied to the storage node to transform the selectors from an initial state having an initial threshold voltage to an operating state having a lower, operating threshold voltage. The stimulus can include a signal having a voltage which does not exceed the operating threshold voltage. To limit peak current consumption, the stimulus can be applied to different subsets of the array, one subset at a time.

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Abstract: A semiconductor memory device includes a control circuit, first wirings, second wirings intersecting the first wirings, and memory cells formed between the first wirings and the second wirings. The control circuit is configured to supply, in a set operation, a set pulse between one of the first wirings and one of the second wirings, supply, in a reset operation, a reset pulse between one of the first wirings and one of the second wirings, and supply, in a first operation, a first pulse between one of the first wirings and one of the second wirings. The first pulse has an amplitude larger than a larger one of an amplitude of the set pulse or an amplitude of the reset pulse, or the same amplitude as the larger amplitude. The first pulse has a pulse width larger than a pulse width of the reset pulse.

Abstract: The present technology provides an electronic device, a memory device, and a method of operating a memory device. The memory device includes a memory cell array including a variable resistance memory cell coupled to a first conductive line and a second conductive line, and a peripheral circuit configured to provide a write pulse or a read pulse to the variable resistance memory cell through the first conductive line. The write pulse is controlled to have one of a first polarity and a second polarity that are opposite to each other. The read pulse is controlled to have a polarity corresponding to a greater value of first and second amorphization start current values of the variable resistance memory cell, the first amorphization start current value being determined by a first pulse having the first polarity, the second amorphization start current value being determined by a second pulse having the second polarity.

Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.

Abstract: A phase-change memory device, comprising: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator comprises a reference array of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current to be lower than said mean value.

Abstract: A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied.

Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.

Abstract: Embodiments of the invention are directed to a method to modify material properties of a functional material of a nanoscale device post-fabrication. The method includes performing one or more conditioning steps. The conditioning steps include applying electrical conditioning signals of predefined form to the nanoscale device, thereby performing an in-situ heating of the functional material and inducing thermally a displacement of atoms, molecules or ions of the functional material of the nanoscale device. Embodiments of the invention further concerns a related electronic device.

Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

Abstract: The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.

Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array, comprising an isolation structure and a plurality of active areas situated in a semiconductor substrate, each of the active areas extending along a length-wise central axis. The isolation structure is situated among the active areas. The active areas are arranged in an array and comprise a plurality of first active areas and a plurality of second active areas. The first active areas are arranged along a first length-wise direction of the active areas. The second active areas are arranged along a second length-wise direction of the active areas. The first active areas are parallel and adjacent to the second active areas, and the first and second active areas are alternately distributed in a direction of word-lines. The first active area having a first width smaller than a second width of the second active area.

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic and 40-50 at % of selenium. The electronic device may include a semiconductor memory device, the semiconductor memory device including a first memory cell that includes a first switching element. The first switching element may include a chalcogenide material including 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic, and 40-50 at % of selenium.

Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

Abstract: An elementary cell includes a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory including an upper electrode, a lower electrode and a layer made of a first active material, designated memory active layer. The selector device includes an upper electrode, a lower electrode and a layer made of a second active material, designated selector active layer. The cell includes a one-piece conductor element including a first branch having one face in contact with the lower surface of the memory active layer in order to form the lower electrode of the memory, a second branch having one face in contact with the upper surface of the selector active layer in order to form the lower electrode of the memory.

Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.