Abstract: An apparatus for modeling a resistive memory device may include a first model circuit and a second model circuit. The first model circuit may include a current-voltage characteristic-embodying circuit, a phase-expressing circuit, and a characteristic-expressing circuit. The current-voltage characteristic-embodying circuit may generate current-voltage characteristic data of the resistive memory device. The phase-expressing circuit may generate phase-expressing data for changing phases of the resistive memory device. The characteristic-expressing circuit may be configured to generate characteristic-expressing data for identifying resistance variation characteristics of the resistive memory device. The characteristic-expressing circuit may transmit the characteristic-expressing data to the current-voltage characteristic-embodying circuit. The second model circuit may include a state-maintaining circuit with a resistive memory device model.

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

Abstract: The operation of a semiconductor memory device may be controlled by a method of operating a memory controller. The operating method may include transmitting a first read command to the semiconductor memory device, and determining whether to generate a discharge command based on the type of command waiting to be transmitted after the first read command.

Abstract: A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.

Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the fir

Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.

Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Various embodiments disclosed herein provide for a neuromorphic logic system, comprising a bitline and a set of wordlines. The neuromorphic logic system also includes a set of resistive switching memory cells, respectively comprising a two-terminal volatile switching device and a two-terminal non-volatile memory device, at each intersection between the bit line and the set of wordlines, wherein the set of resistive switching memory cells are programmed to a set of resistive states and receive a voltage on the bitline above an activation threshold and wherein the magnitude of the voltage applied to the bitline corresponds to a magnitude of a sensory input, resulting in a current that corresponds to the magnitude of the sensor input and the set of resistive states.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, a battery, a first processor, and a second processor. The first processor is configured to execute fault diagnosis on the battery by discharging energy stored in the battery. The second processor is configured to write data cached in the second memory into the first memory and reduce an upper limit of the amount of data to be cached when executing the fault diagnosis than the upper limit of the amount of data to be cached when not executing the fault diagnosis.

Abstract: The present disclosure relates to a structure including a column multiplexor circuit with a plurality of bit line groups to perform a read operation of data using half of a plurality of column selection signals in the column multiplexor circuit, and each of the bit line groups comprises a reference bit line column, a plurality of transistors, and a plurality of bit lines.

Abstract: A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.

Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.

Abstract: A phase change memory cell is provided that includes a phase change material-containing structure sandwiched between first and second electrodes. The phase change material-containing structure has a resistance that changes gradually, and thus may be used in analog or neuromorphic computing. The phase change material-containing structure may contain a plurality of phase change material pillars, wherein each phase change material pillar has a different phase change material composition. Alternatively, the phase change material-containing structure may contain a doped phase change material layer in which a dopant concentration decreases laterally inward from an outermost surface thereof.

Abstract: A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a Gp conductance and a Gm conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which any of the Gp conductance or the Gm conductance have reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.

Abstract: A monolithic integration of phase change material (PCM) switches with a MEMS resonator is provided to implement switching and reconfiguration functionalities. MEMS resonator includes a piezoelectric material to control terminal connections to the electrodes. The PCM is operable between an ON state and an OFF state by application of heat, which causes the phase change material to change from an amorphous state to a crystalline state or from a crystalline state to an amorphous state, the amorphous state and the crystalline state each associated with one of the ON state and the OFF state. A method of fabricating the MEMS resonator with phase change material is provided. A reconfigurable filter system using the MEMS resonators is also provided.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

Abstract: According to one embodiment, a memory device includes a first electrode; a variable resistance layer provided on the first electrode, the variable resistance layer including a chalcogenide compound having a crystal structure; and a second electrode provided on the variable resistance layer. The variable resistance layer includes a first region covering one of an upper surface of the first electrode or a lower surface of the second electrode, and a second region, a concentration of the chemical element being lower in the second region than in the first region.

Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresp

Abstract: A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.

Abstract: A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

Abstract: A memory cell includes a first electrode which extends horizontally over a substrate, a layer stack containing a phase change memory material layer and a threshold switch material layer which wrap around the first electrode, and a second electrode which contains a first vertical portion and a second vertical portion which extend vertically over the substrate and are located on first and second lateral sides of the layer stack.

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

Abstract: An operating method of a memory device is provided. Using a statistical model, a resistance Rdyn of a variable resistor of a memory cell and a variation ?Rdyn of the resistance Rdyn are determined. Based on the resistance Rdyn and the variation ?Rdyn of the resistance Rdyn, an average resistance Rdyn_avg and a beta value of the variable resistor are determined. Then, using the average resistance Rdyn_avg and the beta value, a resistance Ra of an insertion resistor, connected between the memory cell and a power supply generator for generating a power supply voltage VPGM, is determined.

Abstract: According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive effect element including a storage layer and a reference layer; first and second line electrically coupled to the magnetoresistive effect element; and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.

Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.

Abstract: According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.

Abstract: A phase change memory apparatus comprises at least one heating layer; and at least one phase change layer comprising a vanadium dioxide layer, wherein each of the at least one phase change layer is set corresponding to each of the at least one heating layer, the at least one heating layer is configured to heat the at least one phase change layer.

Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.

Abstract: An operating method of a magnetic memory device may include: a first step of retrieving write data to be written to a plurality of magnetic memory cells sharing a bit line according to a write request, the write data including more of a first type of data than a second type of data; a second step of writing the first type of data simultaneously to all cells of the plurality of magnetic memory cells; and a third step of writing the second type of data to a portion of the plurality of magnetic memory cells, the second type of data being different from the first type of data.

Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

Abstract: A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

Abstract: The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.