Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: A spin transfer torque magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer.

Abstract: A method of patterning a substrate includes providing a layer stack comprising a plurality of layers on a base portion of the substrate, where the layer stack includes an electrically conductive layer and a magnetic layer. The method further includes forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, and directing ions towards the layer stack to magnetically isolate and electrically isolate the first protected region from the second protected region.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A magnetic read transducer including a magnetoresistive sensor is described, as well as a fabrication method thereof. The magnetoresistive sensor includes a cap layer overlaying a free layer. The cap layer is situated with a first thickness to absorb boron from the free layer. The magnetoresistive sensor is annealed, and boron is diffused from the free layer and absorbed by the cap layer, improving the magnetic performance of the free layer. The cap layer thickness is then reduced to a second thickness, thereby reducing the shield-to-shield (SS) stack spacing of the magnetoresistive sensor and allowing for increased areal recording density.

Abstract: A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.

Abstract: A novel magnetic memory cell utilizing nanotubes as conducting leads. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry.

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract: A magnetoresistive effect element includes first and second conductive layers, a first magnetic layer between the first and second conductive layers having a magnetization direction that is unchangeable, a second magnetic layer between the first and second conductive layers having a magnetization direction that is changeable, a tunnel barrier layer between the first and second magnetic layers, a nonmagnetic layer between the second magnetic layer and the second conductive layer, and a conductive sidewall film that provides a current path between the second magnetic layer and the second conductive layer that has a lower resistance than a current path through the nonmagnetic layer.

Abstract: A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, COBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC)n where n?2. A second embodiment is represented by (NBC/BC)n/NBC where n?1. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values.

Abstract: A magnetoresistive effect element uses a perpendicularly magnetized material and has a high TMR ratio. Intermediate layers composed of an element metal having a melting point of 1600° C. or an alloy containing the metal on an outside of a structure consisting of a CoFeB layer, an MgO barrier layer, and a CoFeB layer. By inserting the intermediate layers, crystallization of the CoFeB layer during annealing is advanced from an MgO (001) crystal side, so that the CoFeB layer has a crystalline orientation in bcc (001).

Abstract: A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.

Abstract: Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a first ferromagnetic layer, a first nonmagnetic spacer layer proximate to the first ferromagnetic layer, a second ferromagnetic layer proximate to the first nonmagnetic spacer layer, and a first antiferromagnetic layer proximate to the second ferromagnetic layer. For example, the first ferromagnetic layer may comprise a first pinned ferromagnetic layer, the second ferromagnetic layer may comprise a free ferromagnetic layer, and the first antiferromagnetic layer may comprise a free antiferromagnetic layer.

Abstract: A memory cell including information that is stored in the state of a magnetic bit (i.e. in a free layer, FL), where the FL magnetization has two stable states that may be canted (form an angle) with respect to the horizontal and vertical directions of the device is presented. The FL magnetization may be switched between the two canted states by the application of a voltage (i.e. electric field), which modifies the perpendicular magnetic anisotropy of the free layer.

Abstract: Various embodiments may be generally directed to a magnetic sensor constructed with a decoupling layer that has a predetermined first morphology. A magnetic free layer can be deposited contactingly adjacent to the decoupling layer with the magnetic free layer configured to have at least a first sub-layer having a predetermined second morphology.

Abstract: Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

Abstract: According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.

Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer includes a plurality of subregions. Each of the subregions has a magnetic thermal stability constant. The subregions are ferromagnetically coupled such that the free layer has a total magnetic thermal stability constant. The magnetic thermal stability constant is such that the each of the subregions is magnetically thermally unstable at an operating temperature. The total magnetic thermal stability constant is such that the free layer is magnetically thermally stable at the operating temperature. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A memory device includes: a memory including a first magnetic layer having no retaining force and a second magnetic layer having a retaining force, the first magnetic layer and the second magnetic layer being stacked; a first magnet to magnetize the first magnetic layer in a first direction; and a second magnet to apply a magnetic field to a region through which the memory passes when the memory is removed and to magnetize the second magnetic layer in a second direction.

Abstract: A magnetic memory element includes a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer. The second ferromagnetic layer is stacked with the first ferromagnetic layer. The second ferromagnetic layer has a first and second portion. The first and second portion has a changeable direction of magnetization. The second portion is stacked with the first portion in a stacking direction of the first ferromagnetic layer and the second ferromagnetic layer. A magnetic resonance frequency of the second portion is lower than a magnetic resonance frequency of the first portion. The first nonmagnetic layer is provided between the first ferromagnetic layer and the second ferromagnetic layer. The second stacked unit is stacked with the first stacked unit in the stacking direction. The second stacked unit includes a third ferromagnetic layer.

Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and drains connected in series is connected to a source of the select transistor. The bit line is connected a drain of the select transistor. The memory cell array is obtained by forming a memory cell string.

Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.

Abstract: A spin wave element includes a substrate, a multilayer, a detecting portion, and two or more input portions. The multilayer having a lamination direction thereof is formed on the substrate and includes a first ferromagnetic layer. The first ferromagnetic layer has magnetization whose direction is in the lamination direction. The detecting portion and the input portions are formed on the multilayer and separated from each other by a first nonmagnetic layer. In addition, a portion of an outer edge of the multilayer viewed from the lamination direction makes a portion of one ellipsoid. The detecting portion and one of the input portions are located on the long axis of the one ellipsoid. The portion of the one ellipsoid is located on a side of one of the input portions.

Abstract: Various embodiments may be generally directed to a magnetic element capable of optimized magnetoresistive data reading. Such a magnetic element may be configured at least with a magnetoresistive stack that has an electrode lamination having at least a transition metal layer disposed between a magnetically free layer of the magnetoresistive stack and an electrode layer of the electrode lamination.

Abstract: A thin-film magnetic oscillation element includes a pinned magnetic layer, a free magnetic layer, a nonmagnetic spacer layer provided between the pinned magnetic layer and the free magnetic layer, and a pair of electrodes, in which the easy axis of magnetization of the pinned magnetic layer lies in an in-plane direction of the plane of the pinned magnetic layer, and the easy axis of magnetization of the free magnetic layer lies in a direction normal to the plane of the free magnetic layer. Preferably, the relationship between the saturation magnetization Ms and the magnetic anisotropy field Ha of the free magnetic layer satisfies 1.257 Ms<Ha<12.57 Ms. More preferably, the free magnetic layer is composed of an alloy or a stacked film containing at least one element selected from Co, Ni, Fe, and B.

Abstract: A spin transfer torque magnetic random access memory (STTMRAM) element includes a composite fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer. The magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate. The composite layers are made of multiple repeats of a bi-layer unit which consists of a non-magnetic insulating layer and magnetic layer with thicknesses adjusted in a range that makes the magnetization having a preferred direction perpendicular to film plane.

Abstract: A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.

Abstract: A magneto-resistive device having a large output signal as well as a high signal-to-noise ratio is described along with a process for forming it. This improved performance was accomplished by expanding the free layer into a multilayer laminate comprising at least three ferromagnetic layers separated from one another by antiparallel coupling layers. The ferromagnetic layer closest to the transition layer must include CoFeB while the furthermost layer is required to have low Hc as well as a low and negative lambda value. One possibility for the central ferromagnetic layer is NiFe but this is not mandatory.

Abstract: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

Abstract: The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming a non magnetic element; an electrode, a layer forming a ferroelectric element in which the polarization may be oriented in several directions by applying an electric voltage through said layer, said layer forming a ferroelectric element being positioned between the layer forming a lower ferromagnetic element and the electrode; said device being configured so as to allow control of the magnetic configuration of the layers forming ferromagnetic elements by the direction of the polarization in the layer forming a ferroelectric element.

Abstract: A spin logic device which includes an electron confinement layer confining an electron gas in a two-dimensional area (2DEG) subtended by a direction x and a direction y, the latter perpendicular to the former. The spin logic device is configured for the 2DEG to support a persistent spin helix (PSH) formed therein with a given spin component oscillating with periodicity ? along direction x but not oscillating along direction y. Majority logic circuit of the spin logic device includes: at least one input device energizable to create respective local spin-polarizations of the 2DEG in first regions of the confinement layer. The input device is configured to detect in a second region of the confinement layer an average spin-polarization of the 2DEG diffused through resulting PSHs, wherein a projection of a distance between the second region and first regions onto direction x is equal to n?/a, n integer, a equal to 2 or 4.

Abstract: According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel barrier layer formed between the storage layer and the reference layer and containing O, and an underlayer formed on a side of the storage layer opposite to the tunnel barrier layer. The reference layer comprises a first reference layer formed on the tunnel barrier layer side and a second reference layer formed opposite the tunnel barrier layer. The second reference layer has a higher standard electrode potential than the underlayer.

Abstract: A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer.

Abstract: A magnetoresistance element is disclosed. The magnetoresistance element includes a magnetic tunnel junction portion configured by sequentially stacking a perpendicularly magnetized first magnetic body, an insulation layer, and a perpendicularly magnetized second magnetic body. The second magnetic body has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer side interface. A heat assist layer that heats the second magnetic body with a heat generated based on a current flowing through the magnetic tunnel junction portion is further provided.

Abstract: Voltage controlled magneto-electric tunnel junctions (MEJ) and associated memory devices are described which provide efficient high speed switching of non-volatile magnetic random access memory (MeRAM) devices at high cell densities with multiple word access mechanisms, including a burst mode write of multiple words, and a back-to-back read of two words in consecutive clock cycles. In at least one preferred embodiment, these accesses are performed in a manner that prevents any possibility of a read disturbance arising.

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract: A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.

Abstract: The present disclosure concerns a method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense and storage layers; the first and second ferromagnetic layers being arranged such that a dipolar coupling between the storage) and the sense layers is substantially null; the method comprising: switching the second ferromagnetic magnetization by passing a spin-polarized current in the magnetic tunnel junction; wherein the spin-polarized current is polarized when passing in the sense layer, in accordance with the direction of the sense magnetization. The MRAM cell can be written with low power consumption.

Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: A magnetic memory element includes a first magnetic layer, a second magnetic layer, a first intermediate layer, a first magnetic wire, a first input unit, and a first detection unit. The first magnetic layer has magnetization fixed. The second magnetic layer has magnetization which is variable. The first intermediate layer is between the first magnetic layer and the second magnetic layer. The first magnetic wire extends in a first direction perpendicular to a direction connecting from the first magnetic layer to the second magnetic layer and is adjacent to the second magnetic layer. In addition, write-in is performed by propagating a first spin wave through the first magnetic wire and by passing a first current from the first magnetic layer toward the second magnetic layer. Read-out is performed by passing a second current from the first magnetic layer toward the second magnetic layer.

Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element is configured to store a state when electrical current is applied thereto. The perpendicular STTMRAM element includes a magnetization layer having a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL). The direction of magnetization of the first and second free layers each is in-plane prior to the application of electrical current and after the application of electrical current, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.

Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.