Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G1, G2) for the writing voltage and the erasure voltage differ from memory cell to memory cell means that the memory cells can be programmed individually, said memory cells cannot conventionally be erased individually, i.e., selectively in relation to the other memory cells. The reason for this is the large bandwidth of the threshold values (G1) for the erasure voltages, which ranges from a potential (Verasemin) to a potential (Verasemax). The invention proposes a semiconductor memory and a method for operating the latter, in which simultaneous biasing of all the bit lines and word lines and a specific choice of the electrical potentials allow a single memory cell to be erased selectively in relation to the other memory cells.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A multiple-layer serial diode cell and a nonvolatile memory device using the same enable reduction in the number of cell arrays by configuring cell arrays including a nonvolatile ferroelectric capacitor and a serial diode cell as multiple layers. In the nonvolatile memory device, a unit serial diode cell comprising a nonvolatile ferroelectric capacitor and a serial diode switch which does not require an additional gate control signal is positioned between a word line and a bit line, thereby embodying a cross point cell array, which is configured as a multiple layer to reduce the whole chip size.

Abstract: Stacked capacitor memory is realized, wherein a capacitor stores data and a diode serves as an access device instead of MOS transistor, the first terminal is connected to a word line, the second terminal is connected to the first electrode of the capacitor which serves as a storage node while the second electrode is connected to a plate line, the third terminal is floating, and the fourth terminal is connected to a bit line. When write, the storage node is charged or not, depending on the conducting state of the diode which is controlled by the bit line. When read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop which cuts off the current path after latching, thus it reduces active current, minimizes data pattern sensitivity, and also rejects coupling noise.

Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.

Abstract: Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a floating plate capacitor serves as a storage device, wherein the capacitor includes three plates, the first plate is connected to the storage node, the second plate is floating and the third plate is connected to a plate line; when write, the diode determines whether the storage node is coupled or not by raising the plate line; when read, the diode serves as a sense amplifier to detect the storage node voltage whether it is forward bias or not, and the diode sends binary results to a data latch including a current mirror; and the memory is formed on the bulk and SOI wafer.

Abstract: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.

Abstract: A programmable metallization memory cell with a storage region (3) formed from a chalcogenide glass and an electrode (4) which is preferably silver is located at the crossing point of a respective bit line (1) and a respective word line (2). There is a pn junction between the bit lines (1) and the chalcogenide glass.

Abstract: A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.

Abstract: A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line, wherein back channel effect is suppressed adding additional ions in the bottom side of third terminal or applying negative voltage in the well or substrate. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation.

Abstract: In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

Abstract: A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, fourth terminal serves as bit line, at least one of the terminals is formed vertically, which diode is formed from silicon, metal or compound materials. The cell is isolated from well or substrate, and the height of cell is close to that of control circuit. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation.

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: A nonvolatile memory device features a serial diode cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a serial diode chain. The serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.

Abstract: A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor.

Abstract: A nonvolatile memory device features a phase change resistor cell. The nonvolatile memory device using a phase change resistor cell comprises a plurality of phase change resistor cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of phase change resistor cell arrays includes unit phase change resistor cells, and each unit phase change resistor cell is located where a word line and a bit line are crossed in row and column directions. The plurality of word line driving units selectively drive the word lines. The plurality of sense amplifiers sense and amplify data transmitted through the bit lines. Here, the unit phase change resistor cell comprises a phase change resistor and a hybrid switch. The phase change resistor stores a logic data value corresponding to a resistance sate changed by a crystallization state of a phase change material depending on the amount of current supplied from a word line.

Abstract: A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have high signal to noise ratio, high signal margin, and tolerance to process variations, to form a single high performance static memory cell. This new cell has independent read and write paths, which allow for separate optimization of the read (R) and write (W) events, and enable dual-port R/W operation. Furthermore, storage node disturbance during the read and write operations are eliminated, which greatly improves cell stability and scalability for future technologies.

Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling a volume of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a capacitor, and a PNPN nano tube cell having a PNPN diode switch selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: A magnetic sensor using efficient injection of spin polarized electrons at room temperature can be fabricated by forming a semiconductor layer sandwiched between ferromagnets and forming ?-doped layers between the semiconductor layer and the ferromagnets. A sensing method applies a magnetic field to be measured to the semiconductor layer and observes the conductivity of the sensor. The sensing techniques can achieve high magneto-sensitivity and very high operating speed, which in turn provides ultra fast and sensitive magnetic sensors.

Abstract: A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

Abstract: A magnetic sensor based on efficient spin injection of spin-polarized electrons from ferromagnets into semiconductors and rotation of electron spin under a magnetic field. Previous spin injection structures suffered from very low efficiency (less than 5). A spin injection device with a semiconductor layer sandwiched between ?-doped layers and ferromagnets allows for very high efficient (close to 100%) spin polarization to be achieved at room temperature, and allows for high magneto-sensitivity and very high operating speed, which in turn allows devising ultra fast and sensitive magnetic sensors.

Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.

Abstract: A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same time, the bit lines of the second set of memory cells is set up. After completion of reading of the first set of memory cells, the bit lines of this set of memory cells are set up (while the setting up of the bit lines of the second set of memory cells continues). After the bit lines of both sets of memory cells are set up, the second word line is pulsed. At this time, written into both sets of memory cells begins, which comprises data previously read from the first set of memory cells and new data to be written into the second set of memory cells. It is found that this method reduces the overall write time.

Abstract: A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.

Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: A nonvolatile memory includes at least a first electrode (71) and a second electrode (72) provided on a substrate, the first and second electrodes being separated from each other, and a conductive organic thin film (73) for electrically connecting the first and second electrodes. The conductive organic thin film (73) has a first electric state in which it exhibits a first resistance, and a second electric state in which it exhibits a second resistance. A first threshold voltage for a transition from the first electric state to the second electric state, and a second threshold voltage for a transition from the second electric state to the first electric state are different from each other, and either the first electric state or the second electric state is maintained a voltage in a range between the first threshold voltage and the second threshold voltage.

Abstract: A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second terminal of the two terminal semiconductor device coupled to an at least one second control line, wherein the two terminal semiconductor device has a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and has a lower capacitance when the voltage on the first terminal relative to the second terminal is less than the threshold voltage; (3) a read select switch, the control terminal of the read select switch coupled to an at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and (4) a read switch, the control terminal of the read switch couple

Abstract: The present invention discloses a non-volatile ferroelectric cell array circuit using PNPN diode characteristics. The non-volatile ferroelectric cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling an amount of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a ferroelectric capacitor, and a serial PN diode switch having a PNPN diode and a PN diode, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: A nonvolatile memory device features a serial diode cell by effectively arranging a cross point cell array including a nonvolatile ferroelectric capacitor and a serial PN diode chain to reduce the whole memory size. A serial diode cell array including a nonvolatile ferroelectric capacitor and a serial diode switch which does not require an additional gate control signal is positioned on a circuit device region including a word line driving unit, a sense amplifier, a data bus, a main amplifier, a data buffer and an input/output port. An interlayer insulating film separates a cell array region and the circuit device region, thereby reducing the whole chip size.

Abstract: A tunneling diode magnetic junction memory that eliminates the need for a separate semiconductor diode is disclosed. The diode is formed by an insulating layer that is located between a free magnetic layer and a pinned magnetic layer. The present invention further discloses a method of reading the contents of a memory cell in a bi-directional manner in order to extend a storage life of the memory cell.

Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Abstract: A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.

Abstract: A nonvolatile memory device using a serial diode cell comprises a plurality of serial diode switch cell arrays each having a hierarchical bit line structure including a main bit line and a sub bit line. Each of the plurality of sub cell arrays is embodied as a cross point cell, thereby reducing the whole memory size. Specifically, a unit serial diode cell comprising a nonvolatile ferroelectric capacitor and a serial diode switch which does not require an additional gate control signal is located where a word line and a sub bit line are crossed, thereby reducing the whole chip size.

Abstract: An organic switching memory device includes a plurality of first electrode lines; an organic memory layer formed on the plurality of first electrode lines, the organic memory layer having a voltage-current hysteresis characteristic; a semiconductor diode layer stacked on the organic memory layer; and a plurality of second electrode lines formed on the semiconductor diode layer, the plurality of second electrode lines being disposed in a direction so as to intersect the plurality of first electrode lines.

Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed. In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element.

Abstract: A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a phase-changeable or ovonic material. A heating device is disposed to heat the memory material at different rates to a programming temperature. The memory material either has a high resistance or a low resistance after cooling, depending on the heating rate. The heating device has a switching device and a heating element in immediate vicinity to the memory material. The switching device has a field-effect transistor and a drain region of the field-effect transistor forms the heating element. Alternatively, the heating element includes a diode or a diode chain.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.

Abstract: A memory device includes write-once memory; non-volatile memory; and a circuit for writing user data to the write-once memory and at least one of user data and error correction data to the non-volatile memory.

Abstract: A method for configuring an associative array within a molecular-junction-nanowire crossbar, and nanoscale associative arrays configured by the method Keys are encoded as field-effect transistors selectively configured within the molecular-junction-nanowire crossbar, and values associated with keys are encoded as diodes selectively configured at molecular-junction-nanowire-crossbar junctions. Keys input into key registers result in a current signal indicating whether or not the key is stored within the associative array as part of a key/value pair and, if stored in the associative array, the value associated with the input key is output.