Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

Abstract: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include a memory region comprising a plurality of memory cells disposed at respective intersections between a plurality of row lines and a plurality of column lines, the plurality of row lines extending in a first direction, the plurality of column lines extending in a second direction crossing the first direction; first and second row drivers arranged on one side and the other side of the memory region in the first direction, respectively, and driving a common row line corresponding to a row address among the plurality of row lines; and a column driver driving a common column line corresponding to a column address among the plurality of column lines, wherein the first and second row drivers are coupled to the common row line.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.

Abstract: A method for carrying out a refresh of a memory area of a non-volatile memory unit of an embedded system includes refreshing the memory area when a refresh-triggering criterion is satisfied, a check being performed at predefined time intervals to determine whether the refresh-triggering criterion is satisfied, the embedded system being automatically activated and the check being performed if the embedded system is deactivated following the expiration of any of the predefined time intervals.

Abstract: An operating method of a controller includes: searching, by using a predetermined read voltage, a valid word line coupled to a memory cell having a predetermined program status, among word lines coupled to a first open memory block of a memory device when a memory system is powered on after a sudden power off (SPO); and reading data from the memory cell coupled to the valid word line, and writing the read data into a second open memory block.

Abstract: A computer-implemented method for storing and caching data in an all-flash-array includes erasing a TLC-NAND flash cell and programming the cell with a binary value multiple times in sequence corresponding to multiple sequential stages between erasures. The method also includes processing the binary value in relation to a respective threshold voltage at each of the multiple sequential stages. The method further includes storing metadata corresponding to a current stage associated with the number of times the TLC-NAND flash cell has been programmed since being erased.

Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

Abstract: Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

Abstract: Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100-p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.

Abstract: A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the plurality of logical regions are grouped into k number of logical region groups based on their offset values; and a processor suitable for, when receiving a write request for a target logical region, increasing a first access count stored in a first entry of a first table, corresponding to a logical zone including the target logical region, and increasing a second access count stored in a second entry of a second table, corresponding to a logical region group including the target logical region.

Abstract: Provided are modified one-hot (MOH) constructions for WOM codes with low encoding and decoding complexity, that achieve high sum-rates. Features include maximizing writing of data information values for successive rewrites, all-zero and all-one cell state vectors that represent a unique data information value that can be written for many generations, a very high number of writes, and does not sacrifice capacity. One embodiment comprises ordered or unordered MOH code that approaches the upper-bound for large n wits. According to the embodiments, before an erasure is needed, the majority of the wits are encoded, which provides level wearing and maximizes life of cells.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.

Abstract: A system for using bad blocks in a memory system is proposed. The system includes accessing an identification of a plurality of bad blocks and corresponding error codes which, for example, were generated during a manufacturing test and stored on the memory integrated circuit. The system determines which blocks of the plurality of bad blocks to test for being still usable and which blocks of the plurality of bad blocks not to test for being still usable based on corresponding error codes. For each bad block that should be tested, a test from a plurality of tests is chosen based on the corresponding error code in order to determine if the bad block is still usable. Those blocks determined to be still usable are subsequently used to store non-mission critical information.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A storage device includes memories and a controller. The controller controls first and second program operations on the memory. When a temperature of the memory is lower than a reference value, the controller controls execution of the first program operation. When the temperature of the memory is equal to or higher than the reference value, the controller controls execution of the second program operation which consumes a smaller amount of power than the first program operation. The controller adjusts an operational condition of the memory such that bandwidth on the memory remains equivalent during the first and second program operations.

Abstract: A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K?N, L>1, P?M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

Abstract: A memory system and method is provided. The memory system includes a non-volatile memory, a memory interface, and a code processor. The code processor generates a likelihood value for a first read bit, which is read from a first memory cell, from among read bits contained in a codeword read by the memory interface from the non-volatile memory. For example, the likelihood value can be based on the value of the first read bit and on the value of a second read bit read from a second memory cell adjacent to the first memory cell so as to decode the codeword using the generated likelihood value.

Abstract: A memory system may include a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.

Abstract: An operating method of a memory system including a plurality of memory blocks may include grouping the pages of a selected memory block among the plurality of memory blocks based on a program time, sequentially performing a test read on the groups of the pages, detecting an error in the pages of the test-read groups, and reprogramming a page selected based on a result of the error detection.

Abstract: When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rth1 and when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rth1 or when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth1, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.

Abstract: In solid-state memory, such as flash memory, a section of memory is typically erased prior to each time data is programmed therein. In contrast, systems and methods for programming a solid-state memory device with writes from different data sets without an intervening erase are disclosed. For example, the memory device may first erase a block and thereafter program the block with a first data set, with some cells in an erased state and other cells in a non-erased state. After programming the first data set into the block and without erasing the block, the memory device programs the block with a second data set that is at least partially different from the first data set. In this regard, some of the cells, which were in a non-erased state after programming with the first data set, are in an erased state after programming with the second data set.

Abstract: A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.

Abstract: Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.

Abstract: According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.

Abstract: A method for programming a non-volatile memory device includes programming a lower bit in a memory cell included in the non-volatile memory device, reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell, determining a threshold voltage of the memory cell according to a result of reading the lower bit, determining a type of the memory cell using the threshold voltage, and supplying one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.

Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading memory cells based on a default hard-decision voltage level and decoding the obtained hard-bit information; if the decoding fails, reading the memory cells based on default soft-decision voltage levels and then decoding the obtained soft-bit information; if the decoding still fails, reading the memory cells based on first test voltage levels to obtain first soft-bit information and reading the memory cells based on second test voltage levels to obtain second soft-bit information; obtaining a first estimating parameter and a second estimating parameter according to the first soft-bit information and the second soft-bit information, respectively; and updating the default hard-decision voltage level according to the first estimating parameter and the second estimating parameter. As a result, a decoding efficiency can be improved.

Abstract: Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.

Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced.

Abstract: An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.

Abstract: A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node, and an interpretation circuit electrically connected to the node and configured to interpret a voltage at the node and to indicate a resistive state of the memory element based on the voltage at the node. The interpretation circuit includes one or more active devices, one or more passive devices each electrically connected to a respective one of the active devices, and one or more comparators each electrically connected to a respective one of the active devices. Each of the active devices and the passive device electrically connected thereto are configured to provide a voltage level to the respective comparator to which the active device is connected. The comparator(s) are configured to indicate the resistive state of the memory element based on the provided voltage level(s).

Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PRI), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.

Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.

Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

Abstract: A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. One of the characteristics of SLC memory is that data is written more quickly in the SLC memory than the MLC memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation.

Abstract: A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).