Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

Abstract: A memory system includes: two or more memory devices; and a controller suitable for: distributively storing input data in a primary memory device and in a secondary memory device when the input data requested to be stored in the primary device has a greater size than a transfer size for a single interleaving operation of the primary device; and collecting the input data stored in the secondary device into the primary device when the primary and secondary memory devices are in an idle state.

Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Abstract: An erasing method used in a flash memory having memory blocks is illustrated, each of the memory blocks is divided into a plurality of memory sectors, and steps of the erasing method is illustrated as follows. An erasing and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to a memory sector enable signal. An over-erased correcting and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to the memory sector enable signal, wherein the memory sector enable signal is set to be asserted if an over-erased correction is performed on at least one of the memory blocks or at least one of the memory sectors of the memory block.

Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.

Abstract: Disclosed embodiments include a testing system that electrically connects to an integrated circuit (IC) having ferroelectric memory (FRAM) cells. The testing system programs the FRAM cells to a first data state and then iteratively reads the programmed cells at a plurality of reference voltages to identify a reference voltage limit that indicates a first occurrence at which at least one of the cells fails to return the first data state when read. Iteratively reading the cells includes reading each cell at an initial reference voltage at which all the cells return the first data state, and then reading each of the programmed cells at each of the remaining reference voltages by incrementally changing the initial reference voltage in one direction until the reference voltage limit is identified. The testing system sets the reference in the IC at an operating level based on the reference voltage limit.

Abstract: Aspects of the disclosure provide for reducing a temperature of one or more non-volatile memory (NVM) dies of a solid state drive (SSD). The methods and apparatus detect a temperature of one or more NVM dies of a plurality of NVM dies of the SSD, the plurality of NVM dies including at least one parity NVM die, and determine that the one or more NVM dies is overheated when the detected temperature is at or above a threshold temperature. If the detected temperature is at or above the threshold temperature, the methods and apparatus redirect parity data designated for the at least one parity NVM die to the one or more overheated NVM dies. By repurposing the one more overheated NVM dies to store the parity data, the repurposed dies will experience less activity, and therefore, generate less heat without throttling or reducing the workload capability of the dies.

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.

Abstract: A memory management method is provided. The method includes: using a preset read voltage, a left preset read voltage set and a right preset read voltage set corresponding to the preset read voltage to perform a read operation on a target codeword to obtain a hard bit codeword, a left bit codeword and a right bit codeword, respectively; performing iterative decoding operations on each of the hard bit codeword, the left bit codeword and the right bit codeword to identify a trust codeword having a smallest syndrome among the hard bit codeword, the left bit codeword and the right bit codeword; using the hard bit codeword, the left bit codeword, the right bit codeword and the trust codeword to perform a calibration on a log-likelihood ratio table of the iterative operations, so as to update the log-likelihood ratio table to a calibrated log-likelihood ratio table.

Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

Abstract: A semiconductor storage device includes a hookup circuit including first and second circuits connected respectively to first and second bit lines, a first circuit group including a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit, a second circuit group including a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit, and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line. The first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.

Abstract: A circuit includes a memory cell that generates a cell current having a cell current value, a first reference cell that generates a first current having a first current value, and a second reference cell that generates a second current having a second current value. A current generating circuit generates a reference current having a reference current value based on the first current value and the second current value, and a sense amplifier sums, at a comparison node, a third current having the cell current value and a fourth current having the reference current value. A buffer outputs a voltage on the comparison node as an output of the sense amplifier.

Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

Abstract: Methods of operating apparatus include receiving user data for programming to a grouping of memory cells of the apparatus, associating an address of the grouping of memory cells with the user data, determining whether power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, and if power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, programming the address of the grouping of memory cells to a different grouping of memory cells of the apparatus. Methods of operating apparatus further include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.

Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Abstract: A method of operating a semiconductor memory device may include increasing threshold voltage of memory cells by performing an LSB program operation on the memory cells having first state, decreasing threshold voltage of memory cells to be programmed to second state of the memory cells to a level lower than a first level in unit of a memory cell for an MSB program operation, and increasing threshold voltage of memory cells to be programmed to third state of the memory cells to a level higher than a second level, which is higher than the first level, in unit of a memory cell for an MSB program operation.

Abstract: A storage array programming method and device for a resistive random access memory (RAM) are proposed. The resistive RAM comprising a storage array, the storage array comprising a group of storage units to which data is to be written. The programming method comprises: reading the currently stored data in the group of storage units and comparing bit by bit the currently stored data with the data to be written to determine whether the currently stored data is consistent with the data to be written, and generating a data write state according to the determination result; determining the data write state, and by a set operation or a reset operation, writing the data to be written only to the storage units where the currently stored data is inconsistent with the data to be written; checking whether any storage unit having a write failure exists during the set operation or the reset operation; if so, then repeating the previous steps until the writing is completed.

Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

Abstract: An apparatus may include: a memory device suitable for writing data while erasing at least one monitor cell among a plurality of memory cells in a write mode, and reading the at least one monitor cell by supplying a monitor voltage in a monitor mode; and a controller suitable for transmitting a monitor command and address information for reading the at least one monitor cell to the memory device in the monitor mode, and determining whether to perform a reclaim operation based on the values of the at least one monitor cell read by the memory device.

Abstract: A memory system includes a semiconductor memory and a memory controller. The semiconductor memory includes first memory cells, first bit lines connected to the first memory cells, second memory cells, second bit lines connected to the second memory cells, a word line connected to the first and second memory cells, and a driver configured to apply a voltage to the word line. In response to a special read command from the memory controller, the driver sequentially applies, to the word line, first read voltages to read data from the first memory cells, a second read voltage within a voltage range of the first read voltages to read data from the first memory cells, third read voltages to read data from the second memory cells, and a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells.

Abstract: Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells, a word line, bit lines, and a controller. The word line is connected to the memory cells. Each of the lines is connected to the memory cells. In a program operation, while applying a program voltage to the word line, the controller applies a first voltage to a bit line connected to memory cells to which a first data is to be written, applies a second voltage lower than the first voltage to a bit line connected to memory cells to which a second data is to be written, and applies a third voltage lower than the second voltage to a bit line connected to memory cells to which a third data is to be written.

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Abstract: A non-volatile memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include pages including data cells and over-program flag cells configured to represent whether or not the data cells may correspond to an over-programmed cells. The peripheral circuit may be configured to store data in the memory cell array or read the data from the memory cell array. The control logic may be configured to determine whether or not the data cells are programmable when a program command may be received from an external device. The control logic may be configured to program the over-program flag cell corresponding to the data cells when the data cells are not programmable.

Abstract: A data storage device includes a flash memory. The flash memory includes a plurality of weak pages and a plurality of strong pages, wherein each of the strong pages is paired with one of the weak pages, and each of the strong pages has error-correction information of the paired weak page.

Abstract: Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.

Abstract: Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

Abstract: A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.

Abstract: A memory control device and method are provided in the invention. The controller of the memory control device includes a static random access memory (SRAM) which has a first buffer. The controller receives a command from a host device, determines the operation type indicated by the command, and obtains data parameters corresponding to data stored in the SRAM. The DRAM is coupled to the controller and has a second buffer. The controller determines whether the first buffer is enough to store data corresponding to the command according to the data parameters. When the first buffer is not enough to store data corresponding to the command, the controller backs up data corresponding to another operation type to the second buffer, and the controller temporarily stores the data corresponding to the command, and updates the data parameters.

Abstract: A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. The given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

Abstract: A storage device with a memory may optimize the setting of a read threshold or read level. A feedback mechanism may be used responsive to there being a read retry error for providing the read threshold from the read retry. Specifically, recovery from a read failure can provide feedback information for dynamically optimizing read threshold values. Read threshold adjustments may occur each time there is a successful error recovery. The read threshold adjustment scheme may select one logical page or multiple logical pages from a recovered region. If a read threshold is found to be working, this threshold may be part of a feedback message to make an informed adjustment that optimizes the read threshold of other pages.

Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

Abstract: An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.

Abstract: An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.

Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Abstract: A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

Abstract: A method for determining a memory window of at least one resistive random access memory cell, the resistive random access memory cell including a high resistance state and a low resistance state, the passage of the resistive random access memory from an initial state among the high resistance state or the low resistance state to another state then the return to the initial state forming a cycle, the method including: measuring the values of the resistances of the high resistance and low resistance states at a given cycle j, j being an integer; determining the memory window to use during the n cycles following the given cycle j, n being an integer, the memory window being calculated by taking into account at least the resistances of the high resistance and low resistance states at the cycle j.

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

Abstract: Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

Abstract: A current reference circuit includes a current source, a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source, and an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the drain of the first PMOS transistor. The current reference circuit also includes a first resistive element having a first terminal coupled to a source of the NMOS transistor and a gate of the first PMOS transistor and a second terminal coupled to a ground potential, a second PMOS transistor having a drain coupled to the first supply voltage, and a second resistive element having a first terminal coupled to the first terminal of the first resistive element and a second terminal coupled to the gate of the second PMOS transistor.