Abstract: A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: A method of programming a semiconductor device includes performing a Least Significant Bit (LSB) program operation on selected memory cells, performing a soft program operation on the remaining memory cells other than memory cells on which the LSB program operation has been performed, and performing a Most Significant Bit (MSB) program operation on memory cells, selected from among the memory cells on which the LSB program operation has been performed and the memory cells on which the soft program operation has been performed.

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.

Abstract: A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

Abstract: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.

Abstract: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract: An apparatus, system, and method are disclosed for determining a read voltage threshold for solid-state storage media. A data set read module reads a data set from storage cells of solid-state storage media. The data set is originally stored in the storage cells with a known bias. A deviation module determines that a read bias for the data set deviates from the known bias. A direction module determines a direction of deviation for the data set. The direction of deviation is based on a difference between the read bias of the data set and the known bias. An adjustment module adjusts a read voltage threshold for the storage cells of the solid-state storage media based on the direction of deviation.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.

Abstract: A nonvolatile memory device (101) includes a plurality of physical blocks, each of which is provide with a nonvolatile memory (103), a logic/physical address conversion table, a temporary block and a temporary table. The nonvolatile memory (103) includes a plurality of pages which are predetermined writing units, respectively. The logical-physical address conversion table (106) stores correspondence information between logic addresses and physical addresses of data to be stored in the physical blocks. The temporary block is a physical block to store data that are smaller in size than those of the page. The temporary table (107) stores correspondence information between logic addresses and physical addresses with respect to data to be stored in the temporary block.

Abstract: The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range.

Abstract: A flash memory device and method of reading data are disclosed. The method includes; performing a test read operation directed to test data stored in a memory cell array of the flash memory device by iteratively applying a sequence of test read retry operations, wherein each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation, setting an initial read voltage for the flash memory device equal to the minimum test read retry voltage, and thereafter performing a normal read operation directed to user data stored in the memory cell array by iteratively applying a sequence of read retry operations, wherein an initial read retry operation in the sequence of read retry operations uses the initial read voltage.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

Abstract: A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.

Abstract: A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.

Abstract: A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation, at least one bit line coupling circuit configured to couple first bit lines of a nth memory block group to the page buffer group by selectively coupling first bit lines of the first to nth memory block groups in response to bit line coupling signals, and bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.

Abstract: A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions.

Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Abstract: A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory element. The EEPROM and Flash elements are configured to share some of the supporting circuits and can be accessed in parallel.

Abstract: In a memory device, a proportion of at least one cell state in a unit of the memory is determined. A program state of the unit of the memory is determined based on the determined proportion of the at least one cell state. Determining a proportion of at least one cell state in a unit of the memory may be preceded by processing data to be stored in the unit of the memory according to a data value distribution function to produce transformed data having data values conforming to a predetermined distribution and storing the transformed data in the unit of the memory. The distribution function may be configured, for example, to provide a uniform distribution of data values in the unit of the memory.

Abstract: A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.

Abstract: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.

Abstract: A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.

Abstract: In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described device includes a non-volatile memory structure including a first data area, and a second data area that stores information. The information can include a first value corresponding to the first data area, the first value being set responsive to a last programming cycle on the first data area, and a second value indicating a total number of programming or erasing operations on the first data area.

Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract: Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are read at substantially the same time by coupling a selected memory segment, and at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines. Other methods, devices, and systems are also provided.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A non-volatile semiconductor memory is disclosed comprising a memory device including a plurality of memory segments. A program command is issued to the memory device to program a memory segment, and a program time required to execute the program command is saved. An erase command is issued to the memory device to erase the memory segment, and an erase time required to execute the erase command is saved. A wear leveling algorithm is executed for the memory segment in response to the program time and the erase time.

Abstract: According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage.

Abstract: Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units of pages each including memory cells connected in series and to erase data in units of blocks each includes a plurality of the pages. A control gate line is selectively electrically connected to the control gate electrodes of at least one of the blocks. A first switching element includes a current path having ends connected to the control gate line and a ground end. The well is charged, and the first switching element is turned off before the end of the discharge of the well.

Abstract: A system, apparatus, and method to read a memory cell of a memory device is described. The method includes biasing a drain select line (DSL), a source select line (SSL), and unaddressed wordlines of a memory block to a pass voltage to set the DSL, SSL, and unselected word lines into a conducting status; applying a source reading voltage to a source node of the source line; biasing a wordline coupled to the memory cell to a reading voltage; and evaluating the voltage of the bit line. The logical status of the addressed memory cell is based on sensing the bit line voltage during a charging phase of the bit line.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells.

Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell. During writing of information to a plurality of the memory cells connected to an identical word line, the control circuit is configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written.

Abstract: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Abstract: A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

Abstract: A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer.