Bank Or Block Architecture Patents (Class 365/185.11)
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Patent number: 12127361Abstract: The present application provides a memory device.Type: GrantFiled: January 18, 2022Date of Patent: October 22, 2024Assignee: MONTAGE ELECTRONICS (SHANGHAI) COInventors: Christopher Cox, Leechung Yiu, Robert Xi Jin, Zheng Qiu, Leonard Datus, Lizhi Jin
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Patent number: 12124702Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.Type: GrantFiled: September 9, 2022Date of Patent: October 22, 2024Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Hyunkook Park, Sara Choi
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Patent number: 12124743Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.Type: GrantFiled: December 7, 2022Date of Patent: October 22, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Yu-Heng Liu, Yu-Siang Yang, An-Cheng Liu, Wei Lin
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Patent number: 12124370Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.Type: GrantFiled: June 27, 2022Date of Patent: October 22, 2024Assignee: KIOXIA CORPORATIONInventor: Shinichi Kanno
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Patent number: 12124700Abstract: Data may be loaded in a computing device from a non-volatile storage medium using files having a nested structure. An outer file metadata portion may be read from an outer file on the storage medium into RAM. The outer file may include the outer file metadata portion and an outer file data portion. The outer file data portion may then be read from the outer file on the storage medium into the RAM based on the outer file metadata portion. The outer file data portion may be an inner file. The inner file may include an inner file metadata portion and an inner file data portion. Then, the inner file metadata portion may be read from the inner file in the RAM. The inner file data portion may be read from the inner file in the RAM based on the inner file metadata portion.Type: GrantFiled: September 23, 2022Date of Patent: October 22, 2024Assignee: QUALCOMM IncorporatedInventors: Anushka Mihir Nabar, Arun Gothekar, Kishore Batta, Romil Jain
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Patent number: 12118219Abstract: A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.Type: GrantFiled: September 6, 2022Date of Patent: October 15, 2024Assignee: Sandisk Technologies, Inc.Inventors: Shay Benisty, Yossi Yoseph Hassan
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Patent number: 12112816Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.Type: GrantFiled: January 10, 2023Date of Patent: October 8, 2024Assignee: Silicon Motion, Inc.Inventors: Tsu-Han Lu, Hsiao-Chang Yen
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Patent number: 12112806Abstract: In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively.Type: GrantFiled: June 2, 2023Date of Patent: October 8, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yo-Han Lee
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Patent number: 12112826Abstract: A memory device includes a memory group comprising plural memory cells, a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plural memory cells, and a page buffer circuit, coupled to the first memory cell via a bit line. The page buffer circuit includes plural data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plural data latches.Type: GrantFiled: October 13, 2022Date of Patent: October 8, 2024Assignee: SK hynix Inc.Inventor: Kang Woo Park
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Patent number: 12105585Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.Type: GrantFiled: September 17, 2021Date of Patent: October 1, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-chu Oh, Moo-sung Kim, Young-sik Kim, Yong-jun Lee, Jeong-ho Lee
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Patent number: 12105963Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.Type: GrantFiled: September 8, 2022Date of Patent: October 1, 2024Assignee: SanDisk Technologies LLCInventors: Yi Song, Jiahui Yuan, Yanjie Wang
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Patent number: 12101930Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.Type: GrantFiled: May 31, 2022Date of Patent: September 24, 2024Assignee: SK hynix inc.Inventors: Jin Ho Kim, Kwang Hwi Park, Sang Hyun Sung, Sung Lae Oh, Chang Woon Choi
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Patent number: 12101931Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.Type: GrantFiled: July 19, 2023Date of Patent: September 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
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Patent number: 12093140Abstract: A data recovery method, an apparatus, and a solid state drive are provided. The method includes: copying, after an abnormality occurs in the solid state drive, memory data of a first memory space to a solidified area of a second memory space, and then writing address information of the solidified area to a third memory space; recovering, after a controller is reset for the first time, the memory data of the first memory space according to the address information of the solidified area; flushing data of the second memory space into a flash memory space according to the recovered memory data of the first memory space; and performing, after the controller is reset for the second time, data recovery on the solid state drive according to memory data of the flash memory space.Type: GrantFiled: September 23, 2022Date of Patent: September 17, 2024Assignee: SHENZHEN DAPU MICROELECTRONICS CO., LTD.Inventors: Bo Cheng, Shaoquan Liu, Bin Han, Yafei Yang
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Patent number: 12094546Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.Type: GrantFiled: January 31, 2022Date of Patent: September 17, 2024Assignee: SanDisk Technologies LLCInventors: Yi Song, Jiahui Yuan, Yanjie Wang
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Patent number: 12087375Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.Type: GrantFiled: November 5, 2021Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Fulvio Rori, Chiara Cerafogli
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Patent number: 12087390Abstract: Embodiments of the present disclosure relate to a storage device based on a daisy chain topology. According to embodiments of the present disclosure, a storage device may include a plurality of memory package chips each including a plurality of memory dies capable of storing data; and a controller communicating with the plurality of memory package chips and connected to the plurality of memory package chips through one or more daisy chain circuits.Type: GrantFiled: January 28, 2022Date of Patent: September 10, 2024Assignee: SK hynix Inc.Inventors: Jeffrey E. Kwak, Jae Hoon Ko, Jong Joo Lee, Kyung Woo Kim, Hee Ju Kim
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Patent number: 12087369Abstract: A system can include a memory device and a processing device to perform operations that include detecting a transition associated with the memory device from a first power state to a second power state. Responsive to detecting the transition from the first power state to the second power state, the operations include determining a value of a scan frequency in view of the second power state, wherein one or more scan iterations are initiated in accordance with the value of the scan frequency. The operations further include performing one or more block family calibration operations in accordance with the value of the scan frequency.Type: GrantFiled: January 10, 2022Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventor: Vamsi Pavan Rayaprolu
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Patent number: 12087729Abstract: A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.Type: GrantFiled: August 19, 2021Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jen-Yuan Chang
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Patent number: 12080355Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.Type: GrantFiled: September 21, 2021Date of Patent: September 3, 2024Assignee: Silicon Storage Technology, Inc.Inventors: Viktor Markov, Alexander Kotov
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Patent number: 12079076Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.Type: GrantFiled: February 2, 2022Date of Patent: September 3, 2024Inventors: Yoshinori Fujiwara, Vivek Kotti, Christopher G. Wieduwilt, Jason M. Johnson, Kevin G. Werhane
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Patent number: 12073891Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.Type: GrantFiled: February 28, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Violante Moschiano, Jeffrey S. McNeil, James Fitzpatrick, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Patrick R. Khayat
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Patent number: 12058862Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: December 30, 2022Date of Patent: August 6, 2024Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 12058866Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy veType: GrantFiled: March 17, 2021Date of Patent: August 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeryong Sim, Shinhwan Kang, Jeehoon Han
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Patent number: 12056368Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.Type: GrantFiled: August 24, 2022Date of Patent: August 6, 2024Assignee: Kioxia CorporationInventor: Tomoyuki Kantani
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Patent number: 12057161Abstract: The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.Type: GrantFiled: June 23, 2022Date of Patent: August 6, 2024Assignee: SanDisk Technologies LLCInventors: Wei Zhao, Dong-II Moon, Erika Penzo, Henry Chin
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Patent number: 12056367Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.Type: GrantFiled: December 28, 2021Date of Patent: August 6, 2024Assignee: SK HYNIX INC.Inventors: Chung Un Na, Sang Sik Kim
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Patent number: 12050784Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.Type: GrantFiled: April 27, 2022Date of Patent: July 30, 2024Assignee: Micron Technology, Inc.Inventors: Angelo Visconti, Jahanshir Javanifard, Daniele Vimercati
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Patent number: 12046291Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.Type: GrantFiled: September 8, 2022Date of Patent: July 23, 2024Assignee: Kioxia CorporationInventors: Masahiko Iga, Kenro Kikuchi, Nobushi Matsuura
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Patent number: 12046294Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.Type: GrantFiled: June 23, 2022Date of Patent: July 23, 2024Assignee: SanDisk Technologies LLCInventors: Yihang Liu, Xiaochen Zhu, Lito De La Rama, Feng Gao
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Patent number: 12046293Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.Type: GrantFiled: August 19, 2022Date of Patent: July 23, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Chang Lu, Wen-Jer Tsai, Wei-Liang Lin
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Patent number: 12048151Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer.Type: GrantFiled: September 14, 2020Date of Patent: July 23, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Ziqun Hua, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
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Patent number: 12038470Abstract: A test system for a memory card includes a first circuit board. One side of the first circuit board is provided with a plurality of contact groups spaced apart from each other along a row direction. Another side of the first circuit board is provided with slots disposed along the row direction. The test system further includes a second circuit board. The second circuit board is provided with a test circuit, and is inserted into the slot along a direction perpendicular to the first circuit board. The second circuit board provides a test signal to the contact groups.Type: GrantFiled: July 17, 2019Date of Patent: July 16, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Weiwen Pang, Xiaoqiang Li
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Patent number: 12040021Abstract: Embodiments of the present disclosure include a layout of a semiconductor structure, including: a column decoder, wherein the column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region. The first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the second P-type transistor region, and the first N-type transistor region.Type: GrantFiled: June 6, 2022Date of Patent: July 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Huijuan Sun, Jihoon Lee
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Patent number: 12041772Abstract: A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.Type: GrantFiled: August 26, 2021Date of Patent: July 16, 2024Assignee: KIOXIA CORPORATIONInventor: Hanae Ishihara
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Patent number: 12040010Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.Type: GrantFiled: April 21, 2022Date of Patent: July 16, 2024Assignee: SanDisk Technologies LLCInventor: Hiroki Yabe
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Patent number: 12027213Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.Type: GrantFiled: March 19, 2021Date of Patent: July 2, 2024Assignee: Micron Technology, Inc.Inventors: Jie Zhou, Xiangang Luo, Min Rui Ma, Guang Hu
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Patent number: 12020764Abstract: A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.Type: GrantFiled: May 3, 2022Date of Patent: June 25, 2024Assignee: SK hynix Inc.Inventors: Hyung-Sik Won, Hyungsup Kim
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Patent number: 12020763Abstract: A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.Type: GrantFiled: May 3, 2022Date of Patent: June 25, 2024Assignee: SK hynix Inc.Inventors: Hyung-Sik Won, Hyungsup Kim
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Patent number: 12007890Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.Type: GrantFiled: April 26, 2023Date of Patent: June 11, 2024Assignee: THE TRUSTEES OF PRINCETON UNIVERSITYInventors: Naveen Verma, Hossein Valavi, Hongyang Jia
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Patent number: 12002522Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.Type: GrantFiled: May 13, 2022Date of Patent: June 4, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Tao-Yuan Lin, I-Chen Yang, Yao-Wen Chang
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Patent number: 12002512Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.Type: GrantFiled: March 31, 2022Date of Patent: June 4, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Changyeon Yu, Pansuk Kwak, Daeseok Byeon
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Patent number: 12002514Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.Type: GrantFiled: March 28, 2022Date of Patent: June 4, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Won Park, Won-Taeck Jung, Han-Jun Lee, Su Chang Jeon
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Patent number: 11995319Abstract: In certain aspects, a memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row of the rows of the memory cells based on a current data page. Each memory cell is set to one of 2N levels corresponding a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, N?1 data storage units, and a multipurpose storage unit. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page.Type: GrantFiled: November 22, 2022Date of Patent: May 28, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jialiang Deng
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Patent number: 11989421Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.Type: GrantFiled: August 19, 2021Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Ezra E. Hartz, Nicolas Soberanes, Joseph A. De La Cerda, Benjamin Rivera, Bruce J. Ford
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Patent number: 11990191Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.Type: GrantFiled: February 16, 2022Date of Patent: May 21, 2024Assignee: SK hynix Inc.Inventor: Hyung Jin Choi
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Patent number: 11984167Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: October 17, 2022Date of Patent: May 14, 2024Assignee: Kioxia CorporationInventor: Hiroyuki Nagashima
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Patent number: 11983403Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.Type: GrantFiled: October 2, 2020Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventor: Neal A. Galbo
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Patent number: 11977758Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.Type: GrantFiled: August 12, 2022Date of Patent: May 7, 2024Assignee: Micron Technology, Inc.Inventors: Deping He, Caixia Yang
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Patent number: 11972808Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.Type: GrantFiled: February 8, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Abhijith Prakash, Xiang Yang