Bank Or Block Architecture Patents (Class 365/185.11)
  • Patent number: 10978145
    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Biswajit Ray, Peter Rabkin, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
  • Patent number: 10978465
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Yu Jin Seo, Jun Eon Jin
  • Patent number: 10977174
    Abstract: A request to add content to a system data structure can be received. A first set of blocks of a common pool of blocks are allocated to the system data structure and a second set of blocks of the common pool of blocks are allocated to user data. A determination can be made as to whether a garbage collection operation associated with the first set of blocks of the common pool allocated to the system data structure satisfies a garbage collection performance condition. Responsive to determining that the garbage collection operation satisfies the garbage collection performance condition, a block from the common pool can be allocated to the first set of blocks allocated to the system data structure.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Patent number: 10971487
    Abstract: A semiconductor memory device includes a cell wafer including a first plane and a second plane which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells; and a peripheral wafer including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively. The cell wafer includes, on one surface thereof bonded to the peripheral wafer, a first pad which is coupled in common with the first plane and the second plane, and the peripheral wafer includes, on one surface thereof bonded to the cell wafer, a second pad which is coupled with the row decoder and is bonded to the first pad.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Soo-Nam Jung
  • Patent number: 10964638
    Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Soo Kim
  • Patent number: 10964391
    Abstract: The present invention relates to a programming circuit and a programming method of a flash memory, the programming circuit includes a programming transistor and a storage cell connected in series, a gate of the programming transistor is connected to a word line, a gate of the storage cell is connected to a control gate, one end of the programming transistor is connected to a bit line, the other end of the programming transistor is connected to one end of the storage cell, and the other end of the storage cell is connected to a source line. By programming the flash memory by the programming circuit and method of the present invention, the efficiency of latter stage programming can be improved without increasing channel current, thereby improving the efficiency of the entire programming process, shortening the total programming time, and improving the performance of the flash memory.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 30, 2021
    Inventors: Hongsong Ni, Ming Wang
  • Patent number: 10957681
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Patent number: 10957404
    Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Patent number: 10943662
    Abstract: An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 9, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Jayavel Pachamuthu, Kirubakaran Periyannan
  • Patent number: 10929023
    Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Gary L. Howe, Daniel B. Penney
  • Patent number: 10929252
    Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: February 23, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Juan Manuel Cesaretti, Alejandro Gabriel Milesi
  • Patent number: 10910389
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Takehiro Hasegawa, Koji Sakui
  • Patent number: 10908839
    Abstract: A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventor: Myung Hyun Jo
  • Patent number: 10908843
    Abstract: A memory system includes a memory device comprising a plurality of memory blocks; and a controller suitable for controlling the memory device, wherein the controller comprises a real time clock (RTC) management circuitry suitable for generating a sudden power-off (SPO) occurrence cycle using first and second RTC values when a first SPO occurs, and then comparing the SPO occurrence cycle to a threshold value to determine whether to delay dummy page generation; and a dummy page generation circuitry suitable for generating a dummy page using one or more free pages or an incomplete program page, excluding valid pages, from a memory block, among the plurality of memory blocks, according to the determination result of the RTC manager, the incomplete program page indicating a page in which a program operation is interrupted due to an SPO.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10892000
    Abstract: A semiconductor memory device includes a control circuit configured to charge a first node to a first voltage based on a resistance of a memory cell when first data is stored, write second data after the first node is charged to the first voltage, charge a second node to a second voltage based on a resistance of the memory cell when second data is stored, and determine, based on the first and second voltages, whether the first data is different from the second data. The circuit includes a first element including a first end coupled to the first node, and a second end coupled to a third node between the first and second nodes, a second element including first and second ends coupled to the first node, and a third element including a first end coupled to the second node and a second end coupled to the third node.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 10885987
    Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Andrea D'Alessandro, Tommaso Vali, Giovanni Santin
  • Patent number: 10886003
    Abstract: A semiconductor memory device includes a switching controller, a voltage generator and control logic. The switching controller is connected to a local word line. The voltage generator, connected to the switching controller, is configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller. The control logic is configured to control operations of the voltage generator and the switching controller. The control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Ho Lee
  • Patent number: 10885945
    Abstract: A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gerald John Barkley, Daniele Vimercati, Pierguido Garofalo
  • Patent number: 10878901
    Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonhee Lee, Jiyoung Kim, Jintaek Park, Seong Soon Cho
  • Patent number: 10872669
    Abstract: A semiconductor device includes a bit line, a source line, and a memory string coupled between the bit line and the source line. The memory string includes at least one drain select transistor, a plurality of memory cells, at least one source select transistor, and a dummy transistor coupled between the bit line and the drain select transistor or between the source line and the source select transistor.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 10867680
    Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: DENSO CORPORATION
    Inventors: Koichi Yako, Yoshiaki Nakayama
  • Patent number: 10860417
    Abstract: Methods, systems, and devices for multiple memory die techniques are described. A memory device may include multiple memory dies and may be configured to communicate with a host device. For example, each memory die may be coupled with a set of data pins that includes respective subsets of data pins (e.g., a set of eight data pins having two subsets of four data pins). Further, each memory die may have one or more auxiliary pins used for channel coding information for data communicated over one or more of the subsets of data pins. In some cases, each memory die may include one or more additional auxiliary pins, which may be used for channel coding information for a respective subset of data pins or multiple subsets of data pins. The channel coding information associated with the auxiliary pin(s) may include error detection code information, data coding information, or any combination thereof.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wolfgang Anton Spirkl, Thomas Hein, Peter Mayer, Michael Dieter Richter, Martin Brox
  • Patent number: 10861559
    Abstract: A methodology and structure for selectively erases a group of strings in a vertical NAND memory array to account for the slow to erase memory cells in the inner strands compared to the outer strands in the group. Erase signals can be applied through both the drain side connections and the source side connections in a first step to erase the outer strings. A second erase signal can be applied to the inner strands to erase the inner strands. The second signal can be applied from just the drain side connections or through both the drain side connections and the source side connections. In another embodiment, the erase signals are applied from both the source side connections and the drain side connections to the inner strings and only from the source side connections to the outer strings.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Amul Desai, Jayavel Pachamuthu
  • Patent number: 10860918
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Patent number: 10861870
    Abstract: A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru
  • Patent number: 10854301
    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Ramin Ghodsi, Qiang Tang
  • Patent number: 10854299
    Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson
  • Patent number: 10839913
    Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Katsuaki Isobe, Naohito Morozumi, Go Shikata, Susumu Fujimura
  • Patent number: 10839927
    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a string of series-connected memory cells, discharging the respective access line for a second memory cell of the string of series-connected memory cells to a first voltage level, discharging the respective access line for the particular memory cell to a second voltage level higher than the first voltage level, and discharging the respective access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Cantarelli, Augusto Benvenuti, Massimo Ernesto Bertuccio
  • Patent number: 10832782
    Abstract: A nonvolatile memory device that performs a read operation during which row decoder circuitry applies a turn on voltage to a first ground selection line selected from a plurality of ground selection lines, applies a turn off voltage to at least one second ground selection line selected from the plurality of ground selection lines, the at least one second ground selection line being selected from the plurality of ground selection lines based on a read address associated with the read operation, and applies the turn off voltage to an unselected ground selection line among the plurality of ground selection lines after applying a prepulse voltage to the unselected ground selection line.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jooyong Park
  • Patent number: 10826526
    Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiri Nakanishi, Youhei Fukazawa
  • Patent number: 10818356
    Abstract: A nonvolatile semiconductor memory device includes a selection transistor and a memory transistor that are formed on a well for each of a plurality of memory cells. At a time of a data read from the memory transistor, a first voltage is applied to the well and a source of the memory transistor, and a second voltage is applied to a gate of the selection transistor included in a non-selected memory cell among the plurality of memory cells. The first voltage is smaller than an absolute value of the second voltage.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Satoshi Torii, Shu Ishihara
  • Patent number: 10817223
    Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Sajal Mittal, Sneha Bhatia, Vinayak Ghatawade
  • Patent number: 10818328
    Abstract: A nonvolatile memory device includes a control logic circuit that receives a read command from outside the nonvolatile memory device, a memory cell array which includes a plurality of memory cells connected to a plurality of word lines, an address generator that generates a plurality of addresses based on read information from the outside of the nonvolatile memory device, an address decoder sequentially selects a plurality of pages in at least one word line, which correspond to the plurality of addresses, a page buffer circuit that is connected to the memory cell array through a plurality of bit lines, and prepares a plurality of sequential data from memory cells connected to the selected pages by the address decoder, and an input/output circuit that continuously outputs the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through data lines.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Joon Kim, Eun-Jin Yun, Sanghoan Chang
  • Patent number: 10816597
    Abstract: An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 27, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Huanhui Zhan, Krishna Pentakota, Stefan N. Mastovich
  • Patent number: 10811102
    Abstract: A flash memory storage apparatus and a reading method thereof are provided. The flash memory storage apparatus includes a memory cell array and a memory control circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line. The memory control circuit is coupled to the memory cell array and configured to control a read operation of the memory cell array during the reading period. The reading period includes a pre-charge period and a discharge period. The source line performs a pre-charge operation on the bit line via a signal transmission path during the pre-charge period. The bit line performs a discharge operation on the source line via the same signal transmission path during the discharge period. The signal transmission path includes the memory cell string.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 20, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Chiao Ho
  • Patent number: 10811105
    Abstract: A semiconductor storage device includes a first semiconductor extending above a substrate and including a first part and a second part, a first word line at a first level above the substrate and facing the first part of the first semiconductor, a second word line at the first level above the substrate and facing the second part of the first semiconductor, a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line, and a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 20, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Futatsuyama, Masanobu Shirakawa
  • Patent number: 10803959
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masanobu Shirakawa
  • Patent number: 10803953
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 10803950
    Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
  • Patent number: 10803955
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a plurality of bit lines respectively connected to memory cells; a word line commonly connected to the memory cells; and a control circuit. The control circuit programs a first memory cell of a first state and a second memory cell of a second state by using a first program pulse. The control circuit applies a first voltage to a first bit line connected to the first memory cell, and applies a second voltage lower than the first voltage to a second bit line connected to the second memory cell at a first time within a first period during which the first program pulse is applied. The control circuit applies the second voltage to the first and second bit lines at a second time within the first period.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masashi Yoshida, Naofumi Abiko, Yoshikazu Harada
  • Patent number: 10796771
    Abstract: According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masashi Yamaoka
  • Patent number: 10795576
    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Neal A. Galbo
  • Patent number: 10790006
    Abstract: The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10782344
    Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 22, 2020
    Assignee: Rambus Inc.
    Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
  • Patent number: 10783136
    Abstract: Method for writing objects into an object storage. Performing, on a protocol end point: receiving a client request for inserting an object into the object storage, wherein the object has a name and object data; generating a unique ID (UID) for the object; sending, to a name server (NS), a request for creating a guard entry (GE). The GE has a lifetime that defines when the name-object pair is inserted into the object storage. A request to an object server (OS) atomically creates a Garbage Collection Entry and assigns space for the object data. The GCE has a lifetime that defines when the object data is inserted into the object storage; sending, to the OS, object data for writing to storage; sending, to the NS, a request for writing the name; and sending response to the client, to report success after requests to the NS and the OS are successful.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 22, 2020
    Assignee: Virtuozzo International GmbH
    Inventors: Oleg Volkov, Alexey Kobets, Andrey Zaytsev, Kirill Korotaev, Ludmila Ivanichkina
  • Patent number: 10770155
    Abstract: Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Timothy Fisher, Aaron D. Fry, Van Huynh, Charles A. Keller, Jason Szecheong Ma, Kevin E. Sallese, Adalberto G. Yanes
  • Patent number: 10754586
    Abstract: Provided herein may be a storage device and a method of operating the same. A storage device for protecting the storage device from physical movement may include a nonvolatile memory device, a sensor unit configured to collect information about physical movement of the storage device, and a memory controller configured to perform a device lock operation of protecting data in the nonvolatile memory device, based on a sensor value acquired from the sensor unit.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Soo Kim, Soong Sun Shin
  • Patent number: 10747660
    Abstract: A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Chung Un Na, Byeong Gyu Park
  • Patent number: 10748627
    Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong, Zhengyi Zhang