Bank Or Block Architecture Patents (Class 365/185.11)
  • Patent number: 10354722
    Abstract: An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichiro Ishii
  • Patent number: 10355010
    Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
  • Patent number: 10319738
    Abstract: A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sunghoon Kim
  • Patent number: 10304544
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin, Dong Hyuk Chae
  • Patent number: 10296226
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
  • Patent number: 10290355
    Abstract: In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun Mee Kwon, Ji Seon Kim, Sang Tae Ahn
  • Patent number: 10283203
    Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventor: Jin Yong Seong
  • Patent number: 10283175
    Abstract: The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.
    Type: Grant
    Filed: December 24, 2017
    Date of Patent: May 7, 2019
    Assignees: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC., GIGADEVICE SEMICONDUCTOR (BEIJING) INC., GIGADEVICE SEMICONDUCTOR (HEFEI) INC.
    Inventor: Minyi Chen
  • Patent number: 10283204
    Abstract: In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Min Choi, Dong-Chan Kim, Ae-Jeong Lee, Moo-Rym Choi
  • Patent number: 10276221
    Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
  • Patent number: 10269409
    Abstract: A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Patent number: 10262725
    Abstract: A selective bit-line sensing method is provided. The selective bit-line sensing method includes the steps of: generating a neuron weights information, the neuron weights information defines a distribution of 0's and 1's storing in the plurality of memory cells of the memory array; and selectively determining either the plurality of bit-lines or the plurality of complementary bit-lines to be sensed in a sensing operation according to the neuron weights information. When the plurality of bit-lines are determined to be sensed, the plurality of first word-lines are activated by the artificial neural network system through the selective bit-line detection circuit, and when the plurality of complementary bit-lines are determined to be sensed, the plurality of second word-lines are activated by the artificial neural network system.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 16, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Win-San Khwa, Jia-Jing Chen
  • Patent number: 10261721
    Abstract: A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 16, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Chun Liu, Shih-Chou Juan, Nai-Ping Kuo
  • Patent number: 10236038
    Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Troy A. Manning
  • Patent number: 10224106
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 10222990
    Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: March 5, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Alexander Bazarsky, Grishma Shah, Idan Alrod, Eran Sharon
  • Patent number: 10224092
    Abstract: A semiconductor memory device includes a first memory die, a control circuit, and a signal generator. The first memory die includes at least one charge pump on a memory die. The control circuit is configured to control driving of the at least one charge pump during a time period. The signal generator is configured to generate a control signal that prevents the at least one charge pump of the first memory die not to be driven at a same time with a charge pump in a second memory die different from the first memory die and to apply the generated pump enable control signal to the pump enable unit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Minsang Park
  • Patent number: 10216427
    Abstract: A vehicle device includes a storage unit, a determination unit, and a regulation unit. The storage unit stores a native application execution environment and an external application execution environment, the native application execution environment includes a native application preliminarily installed in the vehicle device and a software group for executing the native application, and the external application execution environment includes an external application acquired from an external device and a software group for executing the external application. The determination unit determines a rewriting amount of the storage unit requested by the external application execution environment. The regulation unit regulates a rewriting operation of the storage unit requested by the external application execution environment based on a determination result determined by the determination unit.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: February 26, 2019
    Assignee: DENSO CORPORATION
    Inventor: Toshifumi Suzuki
  • Patent number: 10217517
    Abstract: A method is provided for operating a memory device. The method includes counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage, comparing the number of first off-cells and the number of second off-cells, and determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jin Yim, Sang-Yong Yoon
  • Patent number: 10218503
    Abstract: Methods, systems, and devices are described for encryption key storage and modification in a data storage device. A portion of an encryption key may be stored in a first storage medium, and one or more bits of the encryption key may be stored in a one-time writable storage location. Data received at the data storage device may be encrypted using the encryption key, and may be stored in a storage medium. In the event that it is no longer desired to allow users to access the encrypted data stored in the storage medium, the one or more bits of the encryption key stored in a one-time writable storage location may be modified. Such modification thereby prevents decryption of the encrypted data and effectively precludes access to the encrypted data.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 26, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: George Christian Cope
  • Patent number: 10210930
    Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: February 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayoshi Nakayama, Yasuo Murakuki, Takafumi Maruyama
  • Patent number: 10204692
    Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiko Kamata, Naofumi Abiko
  • Patent number: 10192620
    Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wandong Kim, Sang-Soo Park, Se Hwan Park, Sang-Wan Nam
  • Patent number: 10192622
    Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 29, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor Kouznetsov, Long Hinh, Bo Jin
  • Patent number: 10186326
    Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazutaka Takizawa, Chao Wang, Masaaki Niijima
  • Patent number: 10186325
    Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Mark Helm, Aaron Yip
  • Patent number: 10176872
    Abstract: A method for operating a semiconductor device includes activating a first selection line coupled to a selected first memory string and deactivating a second selection line coupled to an unselected second memory string, applying a read voltage to a selected word line and a pass voltage to an unselected word line, and equalizing the selected word line and the unselected word line, wherein the second selection line is turned on during the equalizing of the selected and unselected word lines.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: January 8, 2019
    Assignee: SK Hynix Inc.
    Inventor: Jong Won Lee
  • Patent number: 10170188
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10170169
    Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10168938
    Abstract: A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: January 1, 2019
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Liping Chen, Mustafa Eroz, Yanlai Liu, Sri Bhat
  • Patent number: 10163511
    Abstract: A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors of the selected memory block and (2) after the pre-program is completed, a main program of sequentially selecting the plurality of memory blocks, programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Sang-In Park
  • Patent number: 10162631
    Abstract: A micro controller unit includes an arithmetic processing unit that executes an arithmetic processing; a peripheral circuit unit that outputs an event signal, which is a trigger for start of the arithmetic processing, based on an operation state; and a data access control unit. When an instruction to access the data designated by the first address is received from the arithmetic processing unit, the data access control unit selectively executes, depending on the event signal input from the peripheral circuit unit: a processing of instructing the data storage unit to access data designated by a first address indicating a storage location of the data on the data storage unit; and a processing of processing of converting the first address and instructing the data storage unit to access data designated by a second address, which is associated with the first address and is different from the first address.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: December 25, 2018
    Assignee: Sanken Electric Co., LTD.
    Inventor: Takanaga Yamazaki
  • Patent number: 10157643
    Abstract: Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a different configuration from other portions of the memory array, may be positioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighboring memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in number of available data in conjunction with the active boundary portions.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 18, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10157675
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Nakai, Noboru Shibata
  • Patent number: 10153051
    Abstract: A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 11, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong, Yen-Lung Li
  • Patent number: 10153040
    Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Hari Giduturi, Mingdong Cui
  • Patent number: 10152262
    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 10147490
    Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: December 4, 2018
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Francesca Grande, Francesco La Rosa, Gianbattista Lo Giudice, Giovanni Matranga
  • Patent number: 10146442
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 4, 2018
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
  • Patent number: 10147501
    Abstract: A data storage device may consist of a non-volatile memory connected to a selection module. The non-volatile memory can have a rewritable in-place memory cell that has a read-write asymmetry. The selection module can dedicate a portion of the non-volatile memory to a data map that can be self-contained along with reactively and proactively altered by the selection module.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 4, 2018
    Assignee: Seagate Technology LLC
    Inventors: David S. Ebsen, Mark Ish, Timothy Canepa
  • Patent number: 10147737
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a select gate; a first insulating film; and a semiconductor film provided in the stacked body and in the substrate. The select gate includes a first portion provided on the substrate and spreading on a first plane crossing a stacking direction of the stacked body, and a second portion provided in the substrate and provided integrally with the first portion. The first insulating film is provided between the select gate and the substrate.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuru Sato
  • Patent number: 10147734
    Abstract: A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 4, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Roni Varkony, Yoram Betser
  • Patent number: 10140042
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Neil Buxton
  • Patent number: 10141066
    Abstract: A memory device including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10141065
    Abstract: A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 27, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kobi Danon, Yoram Betser, Uri Kotlicki, Arieh Feldman
  • Patent number: 10133500
    Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform two or more operations with respect to data units. The operations include: a second read operation, different from the first read operation, that retrieves a data unit to be read based at least in part on an address of a data block containing the data unit to be read, and a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 20, 2018
    Assignee: Ab Initio Technology LLC
    Inventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
  • Patent number: 10134452
    Abstract: According to one embodiment, a memory arrangement is described a memory including a memory cell and a sense amplifier coupled to the memory cell having a node whose potential depends on the difference between a current through the memory cell and a reference current, a detection circuit configured to generate a signal representing whether the current through the memory cell is above or below the reference current based on the potential of the node and a limitation circuit configured to receive the signal and to limit the change of the potential of the node caused by the difference between the current through the memory cell and the reference current in response to the signal.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventor: Ulrich Loibl
  • Patent number: 10134750
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Patent number: 10121544
    Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi, Toru Tanzawa
  • Patent number: 10109355
    Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cell groups, the memory cell groups including a first memory group including first memory cells, and a control circuit configured to execute a first write operation targeting the first memory cells in a first mode in which the control circuit executes at least a first programming operation on the first memory cells followed by a multiple number of first verification operations to verify the first programming operation, and then in a second mode, in which the control circuit executes a second programming operation on the first memory cells followed by a second verification operation to verify the second programming operation. A programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Osamu Nagao