Abstract: Implementations provide a memory, a method for operating a memory, and a memory system. The discloses method can comprises: applying a multi-plane programming scheme to simultaneously perform programming operations on at least two memory planes of the memory device; and in response to determining that an exceptional memory plane of the at least two memory planes has a programming failure, switching to a single-plane programming scheme to sequentially perform programming operations on the at least two memory planes.

Abstract: A memory device comprises: N planes each including a plurality of memory cells, a signal generation block suitable for: selecting a control code corresponding to a selection signal from N control codes respectively corresponding to the N planes, and generating an operation control signal by decoding the selected control code, N operation performing blocks each suitable for performing a predefined operation on a corresponding plane of the N planes according to a value of the operation control signal, a signal transmission block suitable for transmitting the operation control signal to one of the N operation performing blocks through a path corresponding to the selection signal among N paths that connect the signal generation block to the respective N operation performing blocks, and a selection control block suitable for generating the selection signal in response to an input command, an input address and an input clock.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Abstract: A memory circuit and a method for reading a memory circuit are provided. The memory circuit includes reference memory cells and operation memory cells. The method includes reading a selected reference memory cell at a first time to get a first voltage; reading the selected reference memory cell at a second time after the first time to get a second voltage; adjusting a read voltage of the memory cell to be an adjusted read voltage of the memory cell according to the voltage difference between the first voltage and the second voltage; applying the adjusted read voltage on a selected operation memory cell corresponding to the selected reference memory cell; and applying the adjusted read voltage on other selected operation memory cells in a same row of the memory array corresponding to the selected reference memory cell.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: The present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. The semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

Abstract: Implementations described herein relate to a cluster namespace for a memory device. In some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. The memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. The memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

Abstract: An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

Abstract: Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

Abstract: Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.

Abstract: A semiconductor memory device includes a plurality of memory blocks and a contact region. Each of the plurality of memory blocks includes a plurality of memory cells. The contact region is formed between the plurality of memory blocks. The semiconductor memory device uses a first memory block that is not adjacent to the contact region and a second memory block adjacent to the contact region among the plurality of memory blocks differently.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising responsive to receiving a memory access command, determining a portion of the memory device that is referenced by a logical address specified by the memory access command; determining an endurance factor associated with the portion; and modifying, based on a value derived from the endurance factor, a media management metric associated with the portion of the memory device.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: A system and related method operate solid-states storage memory. The system performs a first tuning process that has a first set of tuning options, on a first portion of solid-states storage memory. The system identifies one or more second portions of solid-states storage memory, within the first portion of solid-states storage memory that fail readability after the first tuning process. The system performs a second tuning process that has a differing second set of tuning options, on each of the one or more second portions of solid-states storage memory.

Abstract: Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Abstract: A memory package includes a printed circuit board, a first memory device that is stacked on the printed circuit board, and a second memory device stacked on the first memory device. The first memory device includes a first one-time programmable (OTP) block, the second memory device includes a second OTP block different from the first OTP block, and a horizontal distance from one side of the first memory device to the first OTP block is different from a horizontal distance from one side of the second memory device to the second OTP block.

Abstract: In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.

Abstract: A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Abstract: A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.

Abstract: The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag for indicating a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag being a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition cock to the second data acquisition clock, according to the first data acquisition clock and the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.

Abstract: A semiconductor structure includes an active interposer, a first stack chip module and a second stack chip module. The active interposer includes a substrate, a first control circuit located in a first control area of the substrate, a second control circuit located in a second control area of the substrate, and a communication circuit connected between the first control circuit and the second control circuit. The first stack chip module is stacked vertically on the first control area of the active interposer and the second stack chip module is stacked vertically on the second control area of the active interposer. In addition, a semiconductor structure manufacturing method is also disclosed herein.

Abstract: The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.

Abstract: A semiconductor memory device may include a second conductive type first well, a second conductive type third well, a first conductive type second well, a floating gate and a selection gate. The first well may include a first active region. The third well may include a third active region. The second well may be arranged between the first well and the third well. The second well may include a second active region. The floating gate may be overlapped with the first active region, the second active region and the third active region. The selection gate may be overlapped with the second active region. The selection gate and the floating gate may be arranged side by side. A second overlap area between the second active region and the floating gate may be larger than a third overlap area between the third active region and the floating gate.

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: The present application provides a memory device.

Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.

Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.

Abstract: Data may be loaded in a computing device from a non-volatile storage medium using files having a nested structure. An outer file metadata portion may be read from an outer file on the storage medium into RAM. The outer file may include the outer file metadata portion and an outer file data portion. The outer file data portion may then be read from the outer file on the storage medium into the RAM based on the outer file metadata portion. The outer file data portion may be an inner file. The inner file may include an inner file metadata portion and an inner file data portion. Then, the inner file metadata portion may be read from the inner file in the RAM. The inner file data portion may be read from the inner file in the RAM based on the inner file metadata portion.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.