Bank Or Block Architecture Patents (Class 365/185.11)
  • Patent number: 11328764
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 10, 2022
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 11315646
    Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Bum Kim, Min-Su Kim, Deok-Woo Lee
  • Patent number: 11307918
    Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun chu Oh, Young-Sik Kim, Hee-hyun Nam, Young-geun Lee, Young-jin Cho
  • Patent number: 11309035
    Abstract: Apparatuses and techniques for detecting short circuits in a memory device, and in particular, word line-to-channel short circuits and short circuits between bit line contacts at the top of NAND strings. A short circuit detection operation includes a channel pre-clean phase which discharges a channel of a non-short circuited NAND string while boosting a bit line of a short circuited NAND string, followed by a bit line pre-charge phase which boosts a bit line of the non-short circuited NAND string, followed by a bit line discharge phase which discharges the bit line of the non-short circuited NAND string, followed by a sensing phase which identifies the short circuited NAND strings as being in a programmed or non-conductive state.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Xiaohua Liu, Qianqian Yu
  • Patent number: 11309033
    Abstract: A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyo Kim, Daeseok Byeon, Youngmin Jo, Seungwon Lee
  • Patent number: 11309022
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 19, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11288019
    Abstract: A memory management method for a storage device having a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of physical blocks. The method includes: scanning the plurality of physical blocks to identify one or more bad physical blocks; performing a bad physical block remapping operation on the one or more bad physical blocks to update a virtual block stripe management table; and performing a writing operation under a multiple plane write mode based on the virtual block stripe management table.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 29, 2022
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Hung-Chih Hsieh, Hsiu-Hsien Chu, Yu-Hua Hsiao
  • Patent number: 11289167
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 11276474
    Abstract: A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory, and a controller that stores an on-cell count in the buffer memory, the on-cell count indicating a number of memory cells, which are turned on by a read level applied to a reference word line of each of the plurality of blocks, from among memory cells connected to the reference word line.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunkyo Oh, Sangkwon Moon
  • Patent number: 11276473
    Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Patent number: 11275682
    Abstract: A memory system includes a memory device comprising a memory block having a plurality of pages; and a controller suitable for receiving from an external device an erase request for an erase operation and a first logical address relating to the erase request, and correlating the first logical address to erase information.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Byung-Jun Kim
  • Patent number: 11270778
    Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Han Zhao, Pranav Kalavade, Krishna K. Parat
  • Patent number: 11270760
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array, a plurality of page buffer groups, and a program operation controller. The memory cell array may include a plurality of memory cells. The page buffer groups may be coupled to the plurality of memory cells through a plurality of bit line groups, and may be configured to perform bit line precharge operations on the plurality of bit line groups. The program operation controller may be configured to control the plurality of page buffer groups to perform the bit line precharge operations initiated at different time points during a program operation on the plurality of memory cells, and to adjust an interval between initiation time points of the bit line precharge operations depending on a progress of the program operation.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: In Gon Yang
  • Patent number: 11264086
    Abstract: A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Yeob Cho
  • Patent number: 11257551
    Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Patent number: 11244730
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 8, 2022
    Assignee: Toshiba Memory Corporation
    Inventor: Masanobu Shirakawa
  • Patent number: 11238936
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 11240352
    Abstract: Robust Header Compression (RoHC) compressors and decompressors are provided. A RoHC compressor includes a memory and a processor. The memory stores multiple contexts and multiple codes or program instructions. The processor executes the codes or the program instructions to perform the following steps: receiving a header flow; freeing at least one of the contexts when free space of the memory is insufficient; compressing the header flow; and transmitting the compressed header flow.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 1, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chin Cheng, Xiaolu Ma, Yixin Huang, Runrun Wei, Nengan Gong
  • Patent number: 11238932
    Abstract: In a method of operating a nonvolatile memory device, the nonvolatile memory device includes a memory block that includes a plurality of memory cells and is connected to a plurality of wordlines. A data write command is received. Based on the data write command, a first program operation is performed on some wordlines among the plurality of wordlines connected to the memory block. At least one of the some wordlines on which the first program operation is performed is detected as a no-coupled wordline. Without the data write command, a second program operation is performed on an open wordline on which the first program operation is not performed and adjacent to the no-coupled wordline.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seongho Ahn
  • Patent number: 11232841
    Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Hwan Park, Wan-Dong Kim
  • Patent number: 11222703
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 11, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Patent number: 11204698
    Abstract: A memory controller controls a memory device including a plurality of memory cells. The memory controller may include a workload determination circuit configured to determine a workload state indicating an operating pattern of the memory device based on optimal read voltages for reading the plurality of memory cells when a read operation performed on the memory cells fails; and an operating environment setting circuit configured to set an operating environment of the memory device based on the workload state.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Su Jin Lim
  • Patent number: 11200002
    Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: December 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghyuk Choi, Jaeduk Yu, Sangwan Nam, Sangwon Park, Daeseok Byeon, Bongsoon Lim
  • Patent number: 11189346
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: sub-blocks divided with respect to a buffer page in which buffer cells are included; a voltage generator for, in a program operation of a selected sub-block among the sub-blocks, applying a first pass voltage to unselected word lines connected to the selected sub-block, and applying a second pass voltage lower than the first pass voltage to unselected word lines connected to an unselected sub-block; and a buffer line circuit for selectively turning on or turning off the buffer cells by selectively applying a turn-on voltage or a turn-off voltage to buffer lines connected to the buffer cells. A position of the buffer page is set as a default according to a physical structure of memory cells included in the sub-blocks, and is reset according to an electrical characteristic of the memory cells.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 11188461
    Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Deping He, David Aaron Palmer
  • Patent number: 11189351
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 30, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Sarath Puthenthermadam, Huai-Yuan Tseng
  • Patent number: 11183248
    Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Daniele Balluchi
  • Patent number: 11183249
    Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Yeon Yu, Kui-Han Ko, Il-Han Park, June-Hong Park, Joo-Yong Park, Joon-Young Park, Bong-Soon Lim
  • Patent number: 11170856
    Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: 11164637
    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 2, 2021
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 11158383
    Abstract: An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer; and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: October 26, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Kai Jin Huang, Jin Lyu, Gang Liu
  • Patent number: 11150843
    Abstract: Provided herein may be a storage device and a method of operating the same. A storage device for protecting the storage device from physical movement may include a nonvolatile memory device, a sensor unit configured to collect information about physical movement of the storage device, and a memory controller configured to perform a device lock operation of protecting data in the nonvolatile memory device, based on a sensor value acquired from the sensor unit.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Soo Kim, Soong Sun Shin
  • Patent number: 11139033
    Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 5, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seungwoo Seo, Byeongho Kim, Jaehyun Park, Jungho Ahn, Minbok Wi, Sunjung Lee, Eojin Lee, Wonkyung Jung, Jongwook Chung, Jaewan Choi
  • Patent number: 11138104
    Abstract: A method is described. The method includes tracking a logical saturation value for each of multiple streams having read and write commands directed to a mass storage device, wherein, a stream's logical saturation value is a measurement of how much of the stream's assigned storage resources of the mass storage device contains valid data. The method also includes repeatedly selecting for garbage collection whichever of the multiple streams has a lowest logical saturation value as compared to the other streams.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Shirish Bahirat
  • Patent number: 11132136
    Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhao Cui, Eric Kwok Fung Yuen, Guan Zhong Wang, Xinghui Duan, Hua Chen Li
  • Patent number: 11127465
    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Sang Lee
  • Patent number: 11113210
    Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: September 7, 2021
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Wongyu Shin, Leesup Kim, Youngsuk Moon, Yongkee Kwon, Jaemin Jang
  • Patent number: 11114174
    Abstract: A memory system includes a memory device including a plurality of blocks, a buffer storing degradation information regarding at least one of the plurality of blocks, and a memory controller configured to determine a degradation level of the block corresponding to the read request based on the degradation information, in response to a read request from a host, infer a read level corresponding to the read request based on the degradation level, and read data from the memory device based on the read level.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunkyo Oh, Jinbaek Song, Kangho Roh
  • Patent number: 11112998
    Abstract: The present invention discloses an operation instruction scheduling method and device for a NAND flash memory device. The method comprises: performing task decomposition on the operation instruction of the NAND flash memory device, and sending an obtained task to a corresponding task queue; sending a current task to a corresponding arbitration queue according to a task type of the current task in the task queue; and scheduling a NAND interface for a to-be-executed task in the arbitration queue according to priority information of the arbitration queue. Embodiments of the present invention can efficiently realize operation instruction scheduling of a NAND flash memory device, improve flexibility of operation instruction scheduling of the NAND flash memory device, and improve overall performance of the NAND flash memory device.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 7, 2021
    Assignee: DERA CO., LTD.
    Inventors: Wang Fenghai, Xia Jiexu, Wang Song, Yang Ji, Zhang Jiantao
  • Patent number: 11106532
    Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Patent number: 11100964
    Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan, Yen-Huei Chen
  • Patent number: 11099744
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for writing data in one or more storage units. One of the methods includes obtaining an erasing count for each of multiple storage units, wherein the erasing count equals a total count of erasing operations that have been performed on all blocks of the storage unit. The method further includes identifying one or more of the storage units that satisfy one or more conditions associated with writing data, determining a storage unit that has the smallest erasing count among the identified storage units, and writing the data in the determined storage unit.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 24, 2021
    Assignee: Ant Financial (Hang Zhou) Network Technology Co., Ltd.
    Inventor: Haipeng Zhang
  • Patent number: 11087851
    Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Patent number: 11087853
    Abstract: A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 10, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 11086572
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Patent number: 11081187
    Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 3, 2021
    Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre, Niles Yang
  • Patent number: 11081185
    Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 11074976
    Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Kwang-Ho Kim, Masaaki Higashitani
  • Patent number: 11068183
    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 11069410
    Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: July 20, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Hardwell Chibvongodze, Rajdeep Gautam