Parallel Row Lines (e.g., Page Mode) Patents (Class 365/185.12)
  • Storage device and control method of nonvolatile memory
    Patent number: 8760921
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayasu Kawase, Takaya Suda
  • DATA TRANSMISSION CIRCUIT, MEMORY INCLUDING THE SAME, AND DATA TRANSMISSION METHOD
    Publication number: 20140169094
    Abstract: A data transmission circuit includes an input line selection unit configured to transfer data of a selected input line among a plurality of input lines to an output line, a data sensing unit connected to the plurality of input lines and configured to sense the data of the selected input line, and a data amplification unit configured to amplify data of the output line in response to a data sensing result of the data sensing unit.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventor: Min-Su KIM
  • Storage device and control method of nonvolatile memory
    Patent number: 8755226
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including physical sectors each of which comprises memory cells commonly connected to a word line, each of the memory cells being capable of storing data of not less than 2 bits, each of the physical sectors including pages corresponding to the number of bits storable in the memory cell, and a controller configured to receive a first write command and to write data associated with the first write command to the nonvolatile memory. In a write process using the first write command, the controller is configured to skip an upper page of a physical sector whose lower page is write-accessed by a second write command prior to the first write command.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Shimono, Kazutoshi Noda, Satoshi Sakamoto, Akinori Kamizono
  • Non-volatile memory device and related read method
    Patent number: 8755224
    Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-jin Yun, Sang-chul Kang, Seung-jae Lee
  • Limiting flash memory over programming
    Patent number: 8755229
    Abstract: Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Silvia Beltrami, Angelo Visconti
  • Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
    Patent number: 8750046
    Abstract: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 10, 2014
    Assignee: Apple Inc.
    Inventors: Ofir Shalvi, Naftali Sommer, Uri Perlmutter, Dotan Sokolov
  • Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures
    Patent number: 8750042
    Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 10, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Eran Sharon, Yan Li, Dana Lee, Idan Alrod
  • Experience count dependent program algorithm for flash memory
    Patent number: 8750045
    Abstract: In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 10, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Jianmin Huang, Kulachet Tanpairoj, Chris Nga Yee Avila, Gautam Ashok Dusija
  • Efficient data storage in multi-plane memory devices
    Patent number: 8743603
    Abstract: A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 3, 2014
    Assignee: Apple Inc.
    Inventors: Yoav Kasorla, Eyal Gurgi, Dotan Sokolov, Ofir Shalvi
  • Semiconductor memory device and method of operating the same
    Patent number: 8737128
    Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: May 27, 2014
    Assignee: SK hynix Inc.
    Inventor: Hyung Min Lee
  • SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20140140136
    Abstract: A method of operating a semiconductor device includes storing LSB data in a LSB page included in plural pages of corresponding word line group of a first memory block, generating a data combination signal by combining plural sets of LSB data after the step of storing LSB data, storing the data combination signal in a second memory block, and storing MSB data in a MSB page included in the plural pages.
    Type: Application
    Filed: March 16, 2013
    Publication date: May 22, 2014
    Applicant: SK hynix Inc.
    Inventor: Yong Il JUNG
  • Systems and methods for averaging error rates in non-volatile devices and storage systems
    Patent number: 8730729
    Abstract: A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: May 20, 2014
    Assignee: Densbits Technologies Ltd.
    Inventor: Hanan Weingarten
  • Temporary storage circuit, storage device, and signal processing circuit
    Patent number: 8730730
    Abstract: A temporary storage circuit including a reduced number of transistors is provided. The temporary storage circuit includes storage elements, each of which includes a first transistor and a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A signal potential corresponding to data is input to a gate of the second transistor through the first transistor which is turned on by a control signal input to a gate of the first transistor. Then, the first transistor is turned off by a control signal input to the gate of the first transistor, so that the signal potential is held in the gate of the second transistor. When one of a source and a drain of the second transistor is set to a first potential, the state between the source and the drain of the second transistor is detected, whereby the data is read out.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Method of programming/reading a non-volatile memory with a sequence
    Patent number: 8730725
    Abstract: A method of programming/reading a multi-bit per cell non-volatile memory with a sequence is disclosed. A plurality of less-significant-bit pages are programmed, and a plurality of consecutive most-significant-bit pages of a plurality of consecutive word lines are programmed one after the other in a consecutive order. The most-significant-bit pages through all word lines in at least one memory block of the non-volatile memory are programmed or read after the less-significant-bit pages through all the word lines in the at least one memory block are programmed or read.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 20, 2014
    Assignee: Skymedi Corporation
    Inventors: Han-Lung Huang, Ming-Hung Chou, Chien-Fu Huang, Shih-Keng Cho
  • HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
    Publication number: 20140133236
    Abstract: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: MOSAID Technologies Incorporated
    Inventors: Hong Beom PYEON, Jin-Ki KIM
  • NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
    Publication number: 20140133235
    Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Jin-Ki KIM
  • Data stripes and addressing for flash memory devices
    Patent number: 8724401
    Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 13, 2014
    Assignee: Seagate Technology LLC
    Inventors: Luke William Friendshuh, Mark Allen Gaertner, Jonathan Williams Haines, Timothy Richard Feldman
  • Non-volatile solid state memory-based mass storage device and methods thereof
    Patent number: 8724389
    Abstract: Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 13, 2014
    Assignee: OCZ Storage Solutions, Inc.
    Inventor: Ji-Hyun In
  • Memory device and system with improved erase operation
    Patent number: 8724400
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Jin Lee, Chang-Soo Lee, Joon-Min Park, Hui-Kwon Seo, Qi Wang
  • Semiconductor memory device
    Patent number: 8717816
    Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 6, 2014
    Assignee: Windbond Electronics Corp.
    Inventor: Masaru Yano
  • Magnetic disc controller and method
    Patent number: 8719685
    Abstract: An apparatus includes, in at least one aspect, a plurality of buffers and circuitry configured to store encoded data in one buffer of the plurality of buffers concurrently with storing other data in another buffer of the plurality of buffers and to write the stored encoded data from the one buffer to a storage device concurrently with storing encoded other data in the other buffer, replacing the stored other data in the other buffer.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 6, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Soichi Isono, Minoru Tsukada, Tomoki Oura, Koji Takahashi
  • Method for multi-page programming a non-volatile memory device by simultaneously activating a plurality of selection lines based on programmed data
    Patent number: 8717817
    Abstract: A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Lae Cho, Heeseok Eun, Junjin Kong
  • Semiconductor memory apparatus
    Patent number: 8711640
    Abstract: A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.
    Type: Grant
    Filed: August 27, 2011
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Wook Kwack
  • Single check memory devices and methods
    Patent number: 8711616
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Aaron Yip, Tomoharu Tanaka
  • DATA WRITING METHOD AND DATA STORAGE DEVICE
    Publication number: 20140112069
    Abstract: The invention provides a data writing method and device for a flash memory. According to the method, the flash memory obtains write data to be written to the flash memory, directs the flash memory to write a data page of the write data to a strong page of a target pair page of a target block, and directs the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 24, 2014
    Applicant: Silicon Motion, Inc.
    Inventor: Cheng-Wei LIN
  • Method for non-volatile memory with background data latch caching during read operations
    Patent number: 8705286
    Abstract: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: April 22, 2014
    Assignee: Sandisk Technologies, Inc.
    Inventor: Yan Li
  • Compact sense amplifier for non-volatile memory suitable for quick pass write
    Patent number: 8705293
    Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 22, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan
  • Semiconductor memory device and method of operating the same
    Patent number: 8705287
    Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 22, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seiichi Aritome, Soo Jin Wi, Angelo Visconti, Mattia Robustelli
  • NON-VOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20140104950
    Abstract: A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page. In an erase operation, erase pulses are applied to a block of the memory array to erase data in the block. The non-volatile semiconductor memory performs a pre-program operation before the erase operation and a post-erase operation after the erase operation. In the pre-program operation, each page of the block is programmed according to voltage information relating programming pulses. In the erase operation, data in the block is erased according to the voltage information relating programming pulses.
    Type: Application
    Filed: September 16, 2013
    Publication date: April 17, 2014
    Applicant: Winbond Electronics Corp.
    Inventor: Masaru YANO
  • Systems and methods for improving error distributions in multi-level cell memory systems
    Patent number: 8699269
    Abstract: A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 15, 2014
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Erased State Reading
    Publication number: 20140098610
    Abstract: Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least one neighboring word line.
    Type: Application
    Filed: March 1, 2013
    Publication date: April 10, 2014
    Applicant: SanDisk Technologies Inc
    Inventors: Jianmin Huang, Zhenming Zhou, Gautam Ashok Dusija, Chris Nga Yee Avila, Dana Lee
  • Method and system for adjusting read voltage in flash memory device
    Patent number: 8693252
    Abstract: A method is provided for adjusting a read voltage in a flash memory device. The method includes storing first program count information when first pages of flash memory cells are programmed, the first program count information indicating a number of bits having a first logic value from among bits of data programmed in the first pages of the flash memory cells, and obtaining first read count information by counting a number of bits having the first logic value from among bits of data read from the first pages of the flash memory cells, while reading data from the flash memory cells using read voltages. The read voltages are adjusted based on the difference between the first read count information and the first program count information.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kui-Yon Mun
  • Processors for programming multilevel-cell NAND memory devices
    Patent number: 8693251
    Abstract: In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • METHOD FOR PROGRAMMING AND READING FLASH MEMORY BY STORING LAST PROGRAMMING PAGE NUMBER
    Publication number: 20140092682
    Abstract: The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of the page in the predefined page distribution list of the block while reading the flash memory, and selecting the predefined voltage based on the judged programming times to implement the reading process for raising reading performance.
    Type: Application
    Filed: June 21, 2013
    Publication date: April 3, 2014
    Inventors: Ying-Kai Yu, Jin-Shing Hsieh, Yi-Long Hsiao
  • Method for operating a NAND flash memory device in multiple operational modes
    Patent number: 8687422
    Abstract: A method and device are provided for operating in a special mode using a special mode enable register. In one example, a memory device includes registers in volatile memory and a memory array. At least one of the registers may include a special mode bit that controls a special mode of operation of the memory device.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: April 1, 2014
    Assignee: Micron Technologies, Inc.
    Inventors: Theodore T. Pekny, Victor Y. Tsai
  • Nonvolatile memory device and method of operating the same
    Patent number: 8687423
    Abstract: A nonvolatile memory device includes a control logic configured to generate an internal command in response to an internal clock, a finite state machine configured to generate a plurality of current state signals in a program pulse and verify pulse setup operation for a program operation and a program verify operation in response to the internal command, after a program operation using a program pulse and a program verify operation using a program verify pulse are completed, and a glue logic configured to generate check control signals for checking a plurality of page buffers of the page buffer unit in response to the plurality of current state signals in the setup operation.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventor: Byoung Sung Yoo
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20140085981
    Abstract: A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory block as a work memory area which has a small memory capacity and in which the number of bits to be written at once is small, in which in writing to the code storage memory area a first voltage is supplied to a source line of this memory block, and in writing to the work memory area a second voltage higher than the first voltage is supplied to a source line of this memory block.
    Type: Application
    Filed: August 20, 2013
    Publication date: March 27, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Atsushi TAKEUCHI
  • Error recovery for flash memory
    Patent number: 8681550
    Abstract: A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s).
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yingquan Wu, Marcus Marrow
  • Method of operating semiconductor memory device
    Patent number: 8681544
    Abstract: A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 25, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Kyu Lee
  • Semiconductor memory device
    Patent number: 8675407
    Abstract: A semiconductor memory device includes a plurality of memory cell data holding transistors provided in each block; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to gates of the respective transfer transistors and transferring a desired voltage to the gates of the respective transfer transistors, the block selector electrically connected to gates of the respective transfer transistors and configured to select blocks. A voltage generator generates the voltage to be supplied to the transfer transistors; and a controller controls the row decoder and the voltage generator circuit.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuzuru Namai
  • Non-volatile memory device having configurable page size
    Patent number: 8675408
    Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 18, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Redundancy circuits and operating methods thereof
    Patent number: 8670282
    Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Chun Yang, Yue-Der Chih, Shang-Hsuan Liu
  • NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20140063956
    Abstract: A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches.
    Type: Application
    Filed: February 27, 2013
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventor: Sang O LIM
  • STORAGE DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY
    Publication number: 20140063955
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.
    Type: Application
    Filed: December 3, 2012
    Publication date: March 6, 2014
    Inventors: Masayasu KAWASE, Takaya Suda
  • NOR FLASH MEMORY ARRAY STRUCTURE, MIXED NONVOLATILE FLASH MEMORY AND MEMORY SYSTEM COMPRISING THE SAME
    Publication number: 20140063957
    Abstract: A NOR flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.
    Type: Application
    Filed: November 30, 2012
    Publication date: March 6, 2014
    Inventors: Liyang Pan, Lifang Liu
  • Method for erasing memory array
    Patent number: 8665652
    Abstract: A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 4, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Ping-Hung Tsai
  • Non-volatile memory device and read method thereof
    Patent number: 8665643
    Abstract: Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Tae-Young Kim, Jongsun Sel, Kitae Park
  • Method and apparatus for reading NAND flash memory
    Patent number: 8667368
    Abstract: A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: March 4, 2014
    Assignee: Winbond Electronics Corporation
    Inventors: Anil Gupta, Oron Michael, Robin John Jigour
  • NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
    Publication number: 20140056074
    Abstract: A nonvolatile memory includes a memory cell array including a plurality of nonvolatile memory cells connected to bit lines and word lines crossing the bit lines, a voltage driver configured to provide a word line voltage to the word lines and provide a first voltage during a precharging operation and a second voltage during a sensing operation, based on a voltage setting signal, and a page buffer unit configured to adjust a precharging level of a sensing node connected to a bit line of a page included in a selected memory block of the memory cell array using the first voltage and adjust a sensing level of the sensing node using the second voltage.
    Type: Application
    Filed: July 11, 2013
    Publication date: February 27, 2014
    Inventors: Nam Kyeong KIM, Byoung Sung YOO
  • NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20140056073
    Abstract: A nonvolatile memory device includes a cell array including a plurality of pages, a selection unit configured to select one of the pages in response to a page selection address, an operation control unit configured to read data of a given number of pages adjacent to the selected page and output the read data as backup data, to erase data of the selected page, in response to a page erase command, and to reprogram update data and the backup data in the selected page and the adjacent pages, respectively, and a data storage unit configured to store the backup data.
    Type: Application
    Filed: March 13, 2013
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Gi-Pyo UM, Sang-Sik KIM