Global Word Or Bit Lines Patents (Class 365/185.13)
  • Patent number: 10699789
    Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunyeong Lee, Kyungmoon Kim, Woojae Jang, Chanjong Ju
  • Patent number: 10658044
    Abstract: The semiconductor memory device includes a memory cell array, an address decoder, a switch, and a control logic. The memory cell array includes a plurality of memory blocks having a plurality of memory cells. The address decoder is connected to the memory cell array through row lines. The switch is connected non-memory lines among the row lines. The control logic controls operations of the address decoder and the switch. During an erase operation on memory cells included in a selected memory block among the plurality of memory blocks, the control logic controls the switch to precharge non-memory lines connected to an unselected memory block among the plurality of memory blocks and then float the non-memory lines connected to the unselected memory block.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10534416
    Abstract: A control method for communicating with an external device includes the steps of: when the external device is coupled to a connector, receiving a device existence voltage from the external device; generating a first control signal and a second control signal according to the device existence voltage; coupling a first voltage source or a second voltage source to the connector according to the first control signal, such that a first voltage of the first voltage source or a second voltage of the second voltage source is used as a supply voltage of the external device; and coupling a third voltage source or a fourth voltage source to an output node according to the second control signal, such that a third voltage of the third voltage source or a fourth voltage of the fourth voltage source is used as a tunable output voltage at the output node.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 14, 2020
    Assignee: WIWYNN CORPORATION
    Inventors: Li-Min Chang, Kai Jie Lai, Chia-Hung Yen, Po Yu Chen
  • Patent number: 10403368
    Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 3, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 10170191
    Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Pascucci, Paolo Rolandi
  • Patent number: 10141317
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 10120584
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 10020034
    Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 10, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
  • Patent number: 9865356
    Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: January 9, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Campardo, Salvatore Polizzi
  • Patent number: 9847139
    Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: December 19, 2017
    Assignee: SEAGATE TECHNOLOGY LLP
    Inventors: Zhengang Chen, Erich F. Haratsch
  • Patent number: 9799410
    Abstract: A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 24, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Zhe Wong, Hsin-Ming Chen
  • Patent number: 9773565
    Abstract: A memory retry-read method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a sequence of several retry-read parameter groups according to several weights of the retry-read parameter groups; reading data from a physical programming unit according to a read voltage; if the data are unable to be corrected by a corresponding ECC code, choosing an adjustment retry-read parameter group from the retry-read parameter groups; retrying reading new data from the physical programming unit according to the adjustment retry-read parameter group; if the new data are able to be corrected by the corresponding ECC code, determining the adjustment retry-read parameter group to be an available retry-read parameter group; and adjusting the weight of the available retry-read parameter group.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 26, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9627011
    Abstract: A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.
    Type: Grant
    Filed: July 16, 2016
    Date of Patent: April 18, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Antonino Conte, Francesco La Rosa
  • Patent number: 9614151
    Abstract: A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: April 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David H. Wells
  • Patent number: 9595315
    Abstract: A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Han, Won-Kyung Park, Junhee Lim, Sungho Jang
  • Patent number: 9589647
    Abstract: A semiconductor memory device includes a memory string including a first cells portion and a second cells portion each including a multiple of memory cells, the second cells portion being disposed over the first cells portion, and a control logic configured to control a peripheral circuit such that each of at least two memory cells in a top of the first cells portion and each of at least two memory cells in a bottom of the second cells portion is programmed to have a smaller data bit than remaining memory cells in the first and second cells portions.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 7, 2017
    Assignee: SK hynix Inc.
    Inventors: Jung Ryul Ahn, Ji Hyun Seo, Sung Yong Chung
  • Patent number: 9524972
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 20, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9472292
    Abstract: A semiconductor memory device includes a memory unit including a first memory block and a second memory block, a power supply unit suitable for applying a plurality of operating voltages to one of first global lines or second global lines, a switching circuit suitable for switching the first global lines and first internal global lines in response to a first control signal and switching the second global lines and second internal global lines in response to a second control signal, and a pass circuit suitable for electrically connecting the first internal global lines to word lines and selection lines of the first memory block and electrically connecting the second internal global lines to word lines and selection lines of the second memory block in response to a block selection signal.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 9460792
    Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
  • Patent number: 9449663
    Abstract: A circuit includes a supply voltage circuit, a voltage adjustment circuit, and a timing adjustment circuit. The supply voltage circuit is coupled to a memory device configured to provide a voltage level to the memory device during a write data operation. The voltage adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage level control signal to control one of a plurality of different voltages. At least one of the plurality of different voltages has a voltage level lower than a specified nominal supply voltage level. The timing adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage transition timing control signal to the supply voltage circuit. The supply voltage circuit is configured to provide at least one of the plurality of different voltages to the memory device during the write data operation.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Ping Yang, Cheng Hung Lee, Chia-En Huang, Fu-An Wu, Chih-Chieh Chiu
  • Patent number: 9437598
    Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 6, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 9437256
    Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 6, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Steven M. Bodily
  • Patent number: 9401216
    Abstract: In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 26, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Niles Yang, James Fitzpatrick, Jiahui Yuan
  • Patent number: 9378827
    Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: June 28, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takuya Futatsuyama
  • Patent number: 9343168
    Abstract: Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If the programmed threshold voltage is within a threshold voltage distribution of a plurality of threshold voltage distributions, the memory cell is reprogrammed, and if the programmed threshold voltage is not within a threshold voltage distribution of the plurality of threshold voltage distributions, the memory cell is allowed to remain at the programmed threshold voltage.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mason Jones
  • Patent number: 9330764
    Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 3, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Lee-Yin Lin, Teng-Hao Yeh, Chih-Wei Hu, Chieh-Fang Chen
  • Patent number: 9318172
    Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Bum Kim, Hyung Gon Kim, Chul Ho Lee, Hong Seok Chang
  • Patent number: 9264044
    Abstract: A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Yasuda, Kosuke Tatsumura, Mari Matsumoto, Koichiro Zaitsu, Masato Oda
  • Patent number: 9230663
    Abstract: Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 5, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Ching-Huang Lu, Yingda Dong, Liang Pang, Tien-Chien Kuo
  • Patent number: 9196365
    Abstract: A semiconductor memory device and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array with a string. The string comprises a first dummy memory cell and a second dummy memory cell. A circuit is configured to provide a program voltage and one or more operation voltages to the string during a program operation. Control logic is configured to control the circuit to increase a first threshold voltage of the first dummy memory cell and to increase a second threshold voltage of the second dummy memory cell. The first threshold voltage and a second threshold voltage increase by a hot carrier injection mechanism.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 24, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyoung Jin Park
  • Patent number: 9190152
    Abstract: A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hosono, Tomonori Kurosawa
  • Patent number: 9159386
    Abstract: The semiconductor device includes a command decoder and a voltage generation circuit. The command decoder may be suitable for decoding external command signals to generate a preparation signal and a voltage control signal. The voltage generation circuit may be suitable for generating a read voltage signal used in a read operation and a program voltage signal used in a program operation in response to the preparation signal. In addition, the voltage generation circuit may terminate generation of the read voltage signal and the program voltage signal in response to the voltage control signal.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Byoung In Joo
  • Patent number: 9111627
    Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 18, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Yacov Duzly, Alon Marcu, Yuval Kenan, Yan Li, Man Mui, Seungpil Lee
  • Patent number: 9099189
    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 9070472
    Abstract: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: June 30, 2015
    Assignee: SANDISK IL LTD
    Inventors: Idan Alrod, Eron Sharon, Toru Miwa, Gerrit Jan Hemink, Nima Mokhlesi
  • Patent number: 9064583
    Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 23, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Rajiv Kumar Roy, Disha Singh, Sahilpreet Singh
  • Patent number: 9042175
    Abstract: Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaesung Sim, Bongyong Lee
  • Patent number: 9041203
    Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 26, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
  • Patent number: 9042173
    Abstract: Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 26, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Harvey J. Stiegler, Luan A. Dang
  • Patent number: 9036433
    Abstract: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for driving the second line based on the data from the corresponding first line in a first operation, and a plurality of connection units, each suitable for coupling the third line to the corresponding first line when the corresponding first line is selected in a second operation.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang-Oh Lim
  • Patent number: 9030901
    Abstract: A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyun Heo
  • Patent number: 9025382
    Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9019766
    Abstract: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9019761
    Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors and a plurality of odd pass transistors. Each of the even pass transistors has a, control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line. Each of the odd pass transistors has a control terminal coupled to a respective one of a plurality of odd selection lines, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to an odd global bit line.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 28, 2015
    Assignee: Winbond Electronics Corp.
    Inventor: Im-Cheol Ha
  • Patent number: 9007834
    Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9007833
    Abstract: Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Min Jeon, Weonho Park, Byoungho Kim
  • Patent number: 9001586
    Abstract: A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Deung Kak Yoo
  • Patent number: 8971131
    Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bing Wang
  • Patent number: 8964475
    Abstract: The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. And a first semiconductor layer and a depletion region of a PN junction wrapped up by a gate electrode are enabled to remove GSL and CSL by GIDL memory operation and significantly increase the degree of integration for applying to a neuromorphic technology.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Seoul National University R&DB Foundation
    Inventor: Jong-Ho Lee
  • Patent number: RE45890
    Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaro Itagaki, Yoshiaki Fukuzumi, Yoshihisa Iwata, Ryota Katsumata