Abstract: The present invention provides an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. Further, the present invention provides a method of producing an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines.

Abstract: Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line vol

Abstract: Memory devices and methods, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines.

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.

Abstract: Various embodiments of a semiconductor integrated circuit apparatus are disclosed. In one exemplary embodiment, the apparatus may include a memory cell array having a plurality of memory cell blocks, a plurality of word line selection sections corresponding to the plurality of memory cell blocks, a block selection unit configured to provide a driving signal to the plurality of word line selection sections for driving the plurality of memory cell blocks, and a plurality of global line groups, each corresponding to one of the plurality of word line selection sections. Each of the global line groups may include a plurality of signal lines configured to provide a voltage signal to the corresponding word line selection section.

Abstract: A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.

Abstract: A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

Abstract: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data.

Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

Abstract: Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: Some embodiments of the present invention provide methods of programming memory devices that include an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines. In some method embodiments, potentials of the vertical channels are boosted, followed by selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data. A program voltage is subsequently applied to a selected word plate to thereby program a plurality of cells.

Abstract: A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed.

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract: The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

Abstract: A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

Abstract: A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract: A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Abstract: A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.

Abstract: A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one of the plurality of transistors.

Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Abstract: A NOR flash memory device is programmed by selecting one of a plurality of global bit lines and sequentially selecting a plurality of local bit lines commonly connected with the selected global bit line to supply a program voltage to memory cells.

Abstract: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.

Abstract: A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. A read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.

Abstract: A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.

Abstract: A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.

Abstract: A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N?M/2 largest elements are selected from the ordered sequence.

Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

Abstract: The present invention may be used in systems for non-volatile memory storage of electronic data. A first substrate member may have a first and second surface with a first and second substrate connector spaced apart and attached to the first surface and a first and second spacer element spaced apart and attached to said second surface. A NAND flash controller device may be mounted on the first surface and connected to the substrate connectors and spacer elements. Multiple NAND memory devices may be mounted on the second surface and be connected to the NAND flash controller device. A second substrate member may have a first and second surface with multiple NAND flash memory devices mounted on at least one of the surfaces. The second substrate member may be attached to the spacer elements on the first surface and said multiple NAND flash memory devices may be connected to the NAND flash controller device.

Abstract: A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a control voltage applied to at least one of the word line and the bit line during a program/verify operation in accordance with a location of each one of the plurality of memory blocks within the memory cell array.

Abstract: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

Abstract: A spin-transfer magnetic memory includes a magnetoresistive element having a pinned layer, a free layer and a tunnel insulating layer provided between the pinned layer and the free layer, a bit line connected to one terminal of the magnetoresistive element, a select transistor having a current path whose one terminal is connected to the other terminal of the magnetoresistive element, a source line connected to the other terminal of the current path of the select transistor, and a pulse generation circuit passing a microwave pulse current through the magnetoresistive element, and assisting a magnetization switching of the free layer in a write operation.

Abstract: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Abstract: A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor includes an input node configured to receive a first enable signal; an output node configured to generate the control voltage, a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal, an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled, and a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode.

Abstract: A nonvolatile memory device includes a high voltage generation unit configured to generate a program voltage and a pass voltage, a block selection unit coupled to the high voltage generation unit through global word lines, a memory cell array coupled to the block selection unit through word lines, a discharge unit coupled to the global word lines and configured to change a level of voltage supplied to the global word lines, and a discharge control unit configured to generate a discharge signal, and transfer the discharge signal to the discharge unit in response to the program voltage.

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A nonvolatile memory device includes a plurality of memory blocks, a plurality of erasure detection units provided at the plurality of memory blocks, respectively, and configured to each detect erasure of the respective memory blocks, and a control unit configured to determine that a memory block is a bad memory block when a number of erasure operations performed on the memory block as detected by the respective erasure detection unit is greater than a reference value.

Abstract: A memory cell array of a memory comprises a main memory cell array, including local bit lines, word lines and memory cells, and a selected array, including a global bit line, a bit line transistor (BLT) control line, a transistor and a fixed value memory cell. The local bit lines comprise first and second local bit lines. Each memory cell for storing data corresponds and is connected to one local bit line and one word line. The transistor is coupled to the global bit line, first local bit line and BLT control line, and selectively turns on to connect the global bit line to the first local bit line. The fixed value memory cell coupled to the global bit line, second local bit line, and BLT control line is programmed to a fixed value so that a threshold voltage thereof is greater than a threshold voltage of the transistor.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.

Abstract: A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.