Abstract: A first bit line BLa0 and a second bit line BLb0 are arranged for a single bit line BL0. A memory cell array is divided into a plurality of memory cell array blocks. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. On the further outsides arranged are an electrode wiring 20 for applying a predetermined potential ARGBD and electrode wirings 21 and 22 for applying the control signals DCBLa and DCBLb. A plurality of units, each including the memory cell array block, the control transistors and control signals, are arranged. Main bit lines each passing through these units are extended so that they are connected to the select transistors of each unit pattern. In such a configuration, the capacitive load of bit lines owing to high integration of a non-volatile semiconductor memory is reduced, thereby realizing the high speed operation of the memory.

Abstract: A flash EPROM device (100) is disclosed. During a programming operation, a primary programming voltage circuit (116) drives I/O lines (110) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (118) are located remotely from the primary programming voltage circuit (116) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (116) and the secondary programming voltage circuits (118).