Abstract: A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: Local buses for performing writing/reading of data are provided in correspondence to memory blocks each having a plurality of nonvolatile memory cells, and also circuits for performing writing/reading of data are provided in correspondence to the memory blocks. In addition, data transfer lines for bidirectionally transferring data are provided commonly to the memory blocks, and transfer switch gates for performing data transfer between the memory blocks are provided commonly to the memory blocks. The memory blocks are divided into banks, writing/reading of data on individual memory blocks are performed in units of banks, and parallel execution of writing and reading or of writing/reading and internal transfer is performed. Thus, it is possible to improve data transfer processing efficiency in a nonvolatile semiconductor device.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract: This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

Abstract: A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the memory cells is coupled to respective bitline columns. The circuit further includes a sensed output from one of the bitline columns, and a global bitline coupled to a same respective bitline column of each of the plurality of sub-arrays. Each global bitline includes a voltage swing limiter for limiting a voltage swing of the global bitline, and an n-type transistor. The n-type transistor has a gate, a first terminal, and a second terminal. The gate is coupled to the sensed output, the first terminal is coupled to the global bitline, and the second terminal is coupled to the voltage swing limiter.

Abstract: The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is comprised of a plurality of non-volatile memory cells that are each programmed substantially similarly for each supercell. The supercells are programmed in a complementary fashion. The output state of the apparatus is determined by the state of the supercell to which the output is coupled.

Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

Abstract: A decoder circuit according to the present invention comprises a global row decoder consisted of a first decoding means selected according to a row address signal and a second decoding means to which an output signal of the first decoding means and an erasure signal are input and a local row decoder for selecting each global word line signal outputted from the global row decoder. The local row decoder is consisted of a first and second transistors to the word line signal is input, and a third, fourth and fifth transistors outputting a first voltage supply signal and a second voltage supply signal to a sector word line.

Abstract: A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.

Abstract: Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of the plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to the plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among the plurality of word lines and the plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than said arbitrary word line and the secondary adjacent word lines, and wherein among the

Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.

Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

Abstract: A semiconductor memory device comprising: (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundan

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word lines and bit lines provided so as to cross each other for selecting the memory cell, a row decoder for selecting the word line according to an externally-input row address signal, a column decoder for selecting the bit line according to an externally-input column address signal; and at least one internal voltage generation circuit for applying a voltage required for performing data write/erase operations on the memory array, a plurality of first switch circuits are provided such that each first switch circuit is provided between the at least one internal voltage generation circuit and the row decoder or the column decoder, and a switch selection circuit is provided for selectively operating the plurality of first switch circuits.

Abstract: A semiconductor integrated circuit device includes a global bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which selects one of the first and the second transistors, and a data latch circuit. The data latch circuit includes a data amplifier circuit which amplifies readout data from the first and the second section bit lines, a first data holding circuit which holds readout data and programming data to the first section bit line, and a second data holding circuit which holds readout data and programming data to the second section bit line.

Abstract: A flash memory with a page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry. The global decoder is located outside of the sectors and provides global signals to all sectors via the local circuitry, thus saving area.

Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

Abstract: A nonvolatile semiconductor memory device including a plurality of memory cells each of which has two MONOS memory cells controlled by one word gate and two control gates, the memory cells being arranged in first and second directions. Each two control gate lines connected in common with one sub control gate line have a wide spacing region having a large line-to-line width, a common connection region in which the two lines are connected in common in one line, and a narrow spacing region having a small line-to-line width which is disposed in a region other than the wide spacing region and the common connection region. The wide spacing regions are disposed in the second direction, one on both sides of the common connection region in first and second wiring-only regions in a memory cell array region. The wide spacing region is an enlarged region of bit lines in which a contact is formed. The common connection region is a discontinuous region of the bit line.

Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: A highly integrated semiconductor memory device capable of operating at high speed having a plurality of main word lines which extend along a first direction across memory blocks, and sub word lines disposed in each of the memory blocks and subordinate to each of the main word lines. Sub row decoders are provided corresponding to the memory blocks. Each of the sub row decoders has a plurality of sub word select signal lines extending along a second direction and selects one of the sub word lines. First and second signal supply sections, which supply sub word select signals to the sub word select signal lines disposed in the sub row decoders, are provided on either end in the first direction. A block select signal line extending in the sub row decoder along the second direction is connected with the second signal supply section. The second signal supply section generates the sub word select signal based on the potential of the block select signal line.

Abstract: A semiconductor memory circuit is disclosed, which comprises a plurality of memory cell blocks, a plurality of sub data lines, a first bank region including the plurality of memory cell blocks and the plurality of sub data lines, at least one of second bank region arranged, a plurality of data read lines, a plurality of first amplifier circuits connected to the plurality of data read lines, a plurality of auto data lines, a plurality of second amplifier circuits connected to the plurality of auto data read lines, a plurality of switch circuits provided in correspondence to the plurality of memory cell blocks, wherein data in the plurality of memory cells of the second bank region are readable from the plurality of first amplifier circuits, even when data in the plurality of memory cells of the first bank region is being read from the plurality of second amplifier circuits.

Abstract: An improved memory device column decode apparatus and method is described that incorporates a reduced logic level column address decoder that fully decodes the column address and couples individual sense amplifiers to input or output busses with single pass transistors to provide for increased operation speed and lower sense amplifier resistance. The improved memory device column decode apparatus and method reduces column decode circuit and memory array size allowing for efficient memory array sizing and implementation. Additionally, the improved memory device column decode apparatus and method can incorporate fully decoded column select lines on a separate process layer of the memory array further reducing implementation size.

Abstract: A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit. Multiple local row decoder circuits can, therefore, be controlled by a single global row decoder circuit that provides the separate read and write control signals to each of the local row decoder circuits. By locating the combinatorial logic circuits used for decoding addresses in the global row decoder circuit, rather than in the local row decoder circuits, the local row decoder circuits may have reduced size, thereby allowing further reductions in the size of the flash memory device. For example, in some embodiments according to the invention, a NAND logic circuit used for address decoding is located in the global row decoder circuit, thereby allowing the area allocated to the local row decoder circuit to be reduced.

Abstract: A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: A flash memory with a new page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. The new architecture saves more die area for memory cells and prevents unwanted erasure without affecting the reading time. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry.

Abstract: There is provided a display driver incorporating a RAM in which a plurality of memory cells having a three-port configuration can be provided within an interval of output electrodes thereof, and a display unit and an electronic apparatus utilizing the same. The memory cells include a flip-flop comprised of first and second inverters. A first node of the flip-flop is connected to a CPU bit line and an RGB bit line through an N-type MOS transistor. A P-type MOS transistor and an N-type MOS transistor are connected to a second node of the flip-flop. The N-type MOS transistor is connected to a ground potential level at the source terminal thereof. A set signal for each pixel is supplied to the gate terminal of only the flip-flop associated with the pixel to be written, and the set signal sets the second node at the ground potential level.

Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array region in which a plurality of memory cells are arranged, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates. In reading out data from one of the first and second nonvolatile memory elements of the memory cell, a control voltage of a control-gate-line selection switching element connected to a sub control gate line to which an override voltage is applied, is greater than that of a control-gate-line selection switching element connected to a sub control gate line to which a read voltage is applied.

Abstract: A nonvolatile semiconductor memory device having: a memory cell array region including a plurality of memory cells each of which has two MONOS memory cells and is controlled by a word gate and control gates, are arranged in first and second directions; and first and second select regions. The memory cell array region has a plurality of sub bit lines formed of impurity layers extending to the first and second select regions in the first direction, a plurality of sub control gate lines extending in the first direction, and a plurality of word lines extending in the second direction. Each of the first and second select regions has a sub bit select circuit which selectively connects the plurality of sub bit lines with main bit lines, when the number of the main bit lines is smaller than the number of the sub bit lines.

Abstract: In accordance with an embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of rows and columns of sectors, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. Each of the sectors has a plurality of rows and columns of memory cells. The horizontal global row decoder is configured to select one of the rows of sectors in response to a first set of row address signals. The vertical global row decoder is configured to select one or two adjacent columns of the columns of sectors in response to a second set of row address signals. The plurality of horizontal local row decoders are coupled to the vertical global row decoder and the horizontal global row decoder to select one or two adjacent sectors located at the intersection of the selected row of sectors and the selected one or two adjacent columns of sectors.

Abstract: A contactless NOR-type memory array of the present invention comprises a plurality of integrated floating-gate layers formed on a shallow-trench isolation structure, a plurality of word lines having an interlayer dielectric layer formed on an elongated control-gate layer for each word line, a plurality of common-source bus lines having a silicided conductive layer formed over a flat bed for each common-source line and, a plurality of bit lines with each bit line being integrated with a plurality of silicided conductive islands formed on the common-drain diffusion regions. The contactless NOR-type memory array of the present invention offers a cell size of 4F2, no contact problems for shallow source/drain junction of the cell, lower common-source bus line resistance and capacitance, and better density*speed*power product as compared to existing NAND-type memory array.

Abstract: A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.

Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Abstract: A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

Abstract: In order to achieve a maximally space-saving configuration of a matricial memory arrangement (1), for example in the form of a non-volatile flash memory, which comprises a plurality of memory cells (3) grouped into memory sectors (2), it is proposed to use regular memory cells (4) of this memory arrangement (1) as sector switches for selecting/activating the respective memory sector (2). In order to avoid the effect of high voltages on the threshold voltage of the memory cells (4) configured as sector switches, the “floating gate” (FG) of these memory cells (4) may be short-circuited to the “control gate” (CG).

Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased; after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.

Abstract: The present invention discloses a memory whose power consumption for refresh is reduced to such a level as that of medium and low speed devices, such as SRAM, in its data retention mode. A predetermined number of word lines per block 12a is reduced by a factor n while the number of blocks 12a is increased by a factor n, thereby reducing the number of word lines crossing a bit line by the factor n. The bit line length is reduced and the bit line capacitance is reduced accordingly, so that power consumption of the memory array 16a is reduced.

Abstract: A nonvolatile semiconductor memory device has a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells, is arranged. A plurality of bit lines extend in the first direction, each of the bit lines being connected with each of the plurality of memory cells. The first control gate and the second control gate are formed on one side and the other side of each of the plurality of bit lines, the first control gate being connected with one of two of the memory cells adjacent each other in the second direction and second control gate being connected with the other of the two memory cells. The first and second control gates are respectively formed on either sides of each of the plurality of bit lines. Ends of the first and second control gates are respectively connected by two continuous sections. Each of the bit lines has a projecting section on one end portion.

Abstract: A semiconductor memory device has a memory cell array which includes memory cells arranged in a matrix form on a semiconductor substrate, each of the memory cells including a MISFET which has a source, a drain, a channel body and a gate electrode, each of the memory cells having a first state and a second state; word lines, each of which is connected to the gate electrodes of the memory cells arranged in a first direction; first bit lines, each of which is connected to the drains of the memory cells arranged in a second direction, the bit lines being formed in a first wiring layer located above the semiconductor substrate; and a second bit line which is formed in a second wiring layer located above the first wiring layer, the second bit line being connected to the first bit lines via bit line switches.