Abstract: The preferred embodiments described herein provide a memory device and method for sensing while programming a non-volatile memory cell. In one preferred embodiment, a memory device is provided with a memory cell and a detection circuit. While the memory cell is being programmed, the detection circuit determines whether the memory cell is in a programmed state. If the memory cell is in a programmed state, the programming of the memory cell is terminated. As compared with prior programming approaches, this preferred embodiment reduces programming time and power while increasing programming bandwidth (the number of memory cells that can be programmed per unit time). In another preferred embodiment, a plurality of memory cells along a wordline are programmed simultaneously. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: There is provided a semiconductor memory device, which realizes rewriting of data in the memory cell by applying a potential difference between the gate and the source, or applying a potential difference between the gate and the drain, which is larger than the power supply voltage. This semiconductor memory device is provided with a source line potential control circuit configured to control the source line potential. The source line potential control circuit sets the source line potential at the time of the mode for programming “1” data in a plurality of blocks in one package to a level lower than at the normal data programming mode.

Abstract: A semiconductor memory device includes a plurality of memory cells each having, alternately provided in a word line direction, an active region (channel forming region) comprised of a first conductivity type semiconductor and impurity regions comprised of a second conductivity type semiconductor shared by adjacent memory cells. One embodiment of the method comprises driving control gates capacitively coupled with the borders of the active regions with impurity regions and electrically isolated from the word lines to electrically divide the physical memory cell array into n number of memory cell arrays, and driving the impurity regions and word lines in the same memory cell array to operate in parallel the plurality of memory cells connected to the same word line out of the cell columns.

Abstract: A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost.

Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

Abstract: Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

Abstract: Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and array architecture. The floating-gate memory cells may be programmed using band-to-band tunneling. The floating-gate memory cells may be read using capacitance sensing or forward current sensing techniques.

Abstract: Embodiments relate to a non-volatile semiconductor memory device in which the interface state between the tunnel insulation layer and the floating gate and the interface state between the tunnel insulation layer and the control gate are lower, the operation characteristics are stable, and the data writing/erasing cycle life is long. A non-volatile semiconductor memory device (memory transistor) 400 may include a non-volatile semiconductor memory device with a split-gate structure having a source 16, a drain 14, a gate insulation layer 26, a floating gate 40, an intermediate insulation layer 50 that functions as a tunnel insulation layer, and a control gate 36. The intermediate insulation layer 50 is composed of at least three insulation layers 50a, 50b and 50c. The first and the second outermost layers 50a and 50c of the three insulation layers respectively contact the floating gate 40 and the control gate 36, and are composed of silicon oxide layers that are formed by a thermal oxidation method.

Abstract: A buffer circuit includes a MOSFET source follower (M54) and a floating gate MOSFET (MFG53) connected in series with the phototransistor (PT51) to control current through it at an input circuit node (D53). The source follower (M54) buffers the phototransistor (PT51), having a gate (G54) connected to its emitter (PC51). The floating gate (F53) is programmable with charge to preset the phototransistor current under prearranged illumination conditions to counteract unwanted signal contributions (e.g. fixed pattern noise) or non-optimum circuit characteristics. The floating gate MOSFET (MFG67) may alternatively be connected in series with the source follower output (D65) to control current at an output circuit node. The circuit may be a member of a pixel circuit array and may include programming circuitry (M84, M85) to select it for programming and to isolate it to enable other array members to be programmed.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. The gate heating structure includes a fusible portion in the metal silicide layer formed over the channel region. In an unprogrammed state, the memory cell operates as a conventional MOS transistor, with current flow between the source and drain regions being controlled by a control voltage applied to the metal silicide layer. However, when a programming voltage is applied across the metal silicide, layer, the fusible portion agglomerates, generating intense localized heating. In an embodiment of the invention, the memory cell is an NMOS device. Tie heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device.

Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

Abstract: A multi-level memory cell has a substrate, a first floating gate, a second floating gate and a control gate. A first doped region, a second doped region and a channel region located between the first doped region and the second doped region are provided in the substrate. The first floating gate is located over the channel region near the first doped region. The second floating gate is located over the channel region near the second doped region and isolated from the first floating gate. A control gate is located over the first and the second floating gates. When writing operations are proceeding, the bias voltages of the control gates are the same, and a constant bias voltage is provided on the first doped region or the second doped region depending on which binary states 11, 10, 01 or 00 are to write. Furthermore, the same bias voltage is used on the control gate during writing operation. Thus, the memory per unit chip area is enhanced and the peripheral circuits are simplified.

Abstract: A method for operating a non-volatile memory with symmetrical dual-channels. A programmed step is performed on the non-volatile memory to retain charges in both sides of an ONO layer so that the symmetrical dual-channels are generated and the one-bit writing step is completed. Afterwards, a selected voltage is simultaneously exerted on a first bit line and a third bit line to select a second bit line of the symmetrical dual-channels. Finally, a reading voltage is applied to the second bit line to acquire a reading current which is the sum of total current through the symmetrical dual-channels for increasing the reading speed of the non-volatile memory.

Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

Abstract: A stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized to form a first dielectric layer over the sidewalls of the control-gate layer, a second dielectric layer over the sidewalls of the floating-gate layer, and a thicker oxide layer over each side portion of the active region having a gradedoxide layer formed near two gate edges. An integrated source/drain landing island having a portion formed over a source/drain diffusion region for contact and an extended portion formed over a second dielectric layer and on a graded-oxide layer is acted as a field-emission cathode/anode. The scaled stack-gate flash memory device of the present invention can be programmed and erased through two-tunneling paths or one tunneling path without involving the channel region.

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds the multiple bits in a memory cell. Dual banks of shift registers are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: The method is for programming a memory cell in an array of cells having a plurality of bit lines, each with bit-line coupled cells, and a plurality of word lines, each with word-line coupled cells. A word line-bit line combination identifies a target cell. Each cell has a drain, source, gate and floating gate arrayed upon a base common to the cells, all of which cooperate to establish a floating gate-to-source field in each cell. The method includes the steps of: (a) applying a select signal to a word line and a bit line coupled with the target cell; (b) providing an adjusted signal to the bit-line coupled cells to decrease strength of the floating gate-to-drain field for the bit-coupled cells; (c) programming the target cell; and (d) maintaining the adjusted signal at least until the programming is complete.

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: A programming method comprises the steps of applying a ramp voltage having a first slope to the gate terminal of a selected memory cell to rapidly bring the threshold voltage of the selected cell to an intermediate value; then applying a ramp voltage having a second slope lower than the first, to end programming to the desired final threshold value with high precision. Thereby, when a high threshold value is to be programmed, programming time is reduced; on the other hand, if a low threshold value is to be programmed, the slower ramp voltage is applied right from the start, to prevent possible overprogramming of the cell.

Abstract: A cell array comprising nonvolatile memory cells having; a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said one cell in the X direction, the control gates of the cells arranged along the

Abstract: A nonvolatile memory in which transistors having MFMIS structure each of which is composed by sequentially laminating a floating-gate, a ferroelectric layer and a control gate via a gate insulating film on the surface of a semiconductor substrate between a source area and a drain area formed on the semiconductor substrate are arrayed in a matrix, wherein the control gate is connected to a word line, said source area is connected to a source line and said drain area is connected to a drain line; a floating line composed of writing gates composed so that a capacitor is formed between the writing gate and said floating-gate is provided; a word line and a source line on the same line in said matrix are connected in common; a drain line and a floating line in the same column in said matrix are connected in common; and source/drain voltage and gate voltage can be independently set.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: Structures and methods involving non volatile depletion mode p-channel memory cells with an ultrathin tunnel oxide thicknesses, e.g. less than 50 Å, have been provided. Both the write and erase operations are performed by tunneling and method embodiments are included with the present invention. The floating gate of the depletion mode p-channel memory cell is adapted to hold a fixed charge over a limited range of floating gate potentials or electron energies. For the present invention, there is a range potentials applied to the floating gate for which there are no final nor initial states in the silicon substrate or p+ source region. In this range of potentials there can be no charge leakage, neither a gain nor a charge loss from the floating gate by tunneling or thermally assisted tunneling. In other words the potential of the floating gate can have different states and there will be no change in the charge state, due to leakage currents.

Abstract: Memory cell programming time can be reduced by using a longer initial pulse followed by regular length pulses as needed. Since memory cell programming pulses have raise and fall times, when the voltage applied is less than the programming voltage, and each programming pulse requires a program verify, which increases the programming overhead, replacing the first few regular pulses with a single longer pulse reduces the programming overhead.

Abstract: A semiconductor device comprises a semiconductor body (1) having a region (2) of a first conductivity type adjoining a surface (3) of the semiconductor body (1), which semiconductor body (1) is provided at the surface (3) with a non-volatile memory cell. The memory cell comprises a source (4) and a drain (5) of an opposite, second conductivity type provided in the semiconductor body (1), between which source (4) and drain (5) the surface (3) of the semiconductor body (1) is provided with a floating gate (6) and a select gate (10). The floating gate (6) and the select gate (10) both have a substantially flat surface portion (13) extending substantially parallel to the surface (3) of the semiconductor body (1) and side-wall portions (14) extending substantially transversely to the surface (3) of the semiconductor body (1).

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.

Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: An improved approach to examining program strength of non-volatile latches is disclosed. The program strength is able to be evaluated by inferring floating gate charge of memory elements of the non-volatile latches as indicated by current characteristics of the memory elements. Access to the program charge or the internal currents is facilitated by monitoring circuitry provided integral with the non-volatile latches.

Abstract: Techniques are used to evaluate margin of programmable memory cells. In particular, techniques are used to measure negative erased threshold voltage levels.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells.

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A flash memory device is described. A gate oxide layer is situated on a substrate next to a trench and a floating gate is located on the gate oxide layer. A source region is located in the substrate at the bottom of the trench and a drain region is located on a side of the floating gate. A dielectric layer is on the floating gate, the gate oxide layer and the trench. A control gate is located on the dielectric layer.

Abstract: The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).