Abstract: An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide layer, a charge trapping layer; and a top oxide layer. The bottom oxide layer is no thicker than that which provides margin stability.

Abstract: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

Abstract: In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

Abstract: A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate. The inversion layers are electrically connected to the global bit lines and a memory cell uses the inversion layers as a source and a drain.

Abstract: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

Abstract: The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, first of all, the p-type well is set at 0V. Then, a first inversion layer created by setting the first assist gate at a voltage A is set at a voltage B and the second assist gate is set at a voltage C. Subsequently, a second inversion layer created by setting the third assist gate at a voltage D is set at a voltage E and the control gate is set at a voltage F to inject hot electrons generated on the surface of the p-type well in close proximity to the second assist gate into the second storage node.

Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.

Abstract: An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.

Abstract: A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

Abstract: A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.

Abstract: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to apply, to the control gate of the cell transistor in read, a potential of the same sign as that of a potential applied to the gate of the selector gate transistor.

Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The sneak currents may arise when cells in each of two adjacent I/O groups are sensed (or programmed) at the same time.

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.

Abstract: A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

Abstract: A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations.

Abstract: A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.

Abstract: A split-gate memory cell includes a memory transistor and a select transistor. The memory transistor includes a drain, a source, a control gate and a floating gate. The select transistor includes a drain, a source and a select gate. The source of the select transistor is electrically connected to the drain of the memory transistor. The threshold state of the floating gate of the memory transistor determines the logic output of the memory cell. When the split-gate memory cell is erased or programmed a high voltage is only applied to the control gate and source of the memory transistor. As a result, no high voltage will be placed on any portion of the select transistor and the split-gate memory cell can achieve an increased cycling endurance.

Abstract: An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal of the fuse. A programming voltage can be supplied to the fuse at a second terminal of the fuse; and a logic gate circuit is connected to the gate of the programming transistor. The logic gate circuit is operated at the programming voltage so that the logic gate circuit drives the programming transistor in the efficient saturation region when programming the fuse. The bitcell also includes a fuse-sensing circuit having no more than one transistor. Operation in the efficient saturation region allows the programming transistor to be small. Combined with using no more than one sensing transistor, significant reduction in area of the bitcells on the chip is achieved.

Abstract: A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.

Abstract: A semiconductor device including a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, a detection circuit that refers to an output voltage of the program voltage supply circuit and detects a decrease of the program voltage supplied thereby, a frequency converting circuit that generates the clock signal by converting a frequency of a clock signal generated by an oscillator circuit into a lower frequency when the program voltage supplied by the program voltage supply circuit becomes equal to or lower than a given voltage, and a voltage generating circuit that generates a voltage supplied to a gate of the memory cell by using a clock signal, the frequency of which is converted by the frequency converting circuit. It is therefore possible to make the best use of the ability of the program voltage generating circuit in programming.

Abstract: A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

Abstract: A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.

Abstract: For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.

Abstract: This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.

Abstract: A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.

Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

Abstract: A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.

Abstract: A semiconductor memory device includes: a memory cell array having word lines and bit lines disposed to cross each other, and memory cells disposed at crossings thereof; a controller configured to control operations of the memory cell array; and a word line drive circuit configured to set at least one of unselected word lines in an electrically floating state while driving a selected word line, based on input address and control signals output from said controller.

Abstract: A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.

Abstract: A nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. Each resistance-change portion is of a second conductivity type having impurity concentration lower than that of the first and second main electrode regions. The charge-accumulation portions are provided on the associated resistance-change portions. Each charge accumulation portion has an insulating layer, and is capable of accumulating charge.

Abstract: In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array that are to be programmed, all the electrodes of the cell are grounded. Then, an inhibiting voltage Vn is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or remain at the inhibiting voltage Vn. For all cells in the NVM array that are not selected for programming, the inhibiting voltage Vn is applied to Vr, Ve and Dr and is also applied to Vp, Dp and Vnw.

Abstract: A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask.

Abstract: A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.

Abstract: A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.