Abstract: A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase. The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.

Abstract: A nonvolatile memory device in which an electrically conductive “program assist plate” is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

Abstract: A contacted array of programmable and erasable semiconductor memory devices. Each of the memory devices has a split gate structure, including a source region, a drain region, a channel extending between the source and drain regions, a floating gate extending over a portion of the channel with a first dielectric layer therebetween, a control gate extending over a portion of the floating gate through a second dielectric layer, and a program gate extending above the floating gate with a dielectric layer therebetween. The program gate forms a capacitor with the floating gate with a coupling ratio sufficient to couple a voltage at least as high as the drain voltage to the floating gate, thereby establishing a high voltage at a point in the channel between the control gate and the floating gate and ensuring a high hot-electron injection towards the floating gate.

Abstract: A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.

Abstract: A method of erasing a memory cell that includes a first region and a second region with a channel therebetween that has spillover electrons and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes generating neutralizing holes in the substrate, moving the neutralizing holes to the channel and substantially neutralizing the spillover electrons with the neutralizing holes moved to the channel.

Abstract: A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Abstract: Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.

Abstract: Memory cells are divided into a plurality of series circuit units arranged in matrix fashion and comprising some memory cells connected in series. The memory cells each consist of non-volatile transistors provided with a control gate electrode, a floating gate electrode and an erase gate electrode. Bit lines to which one end of each of the series circuit units of the plurality of series circuit units arranged in one row are connected in common. Column lines are provided in common for the series circuit units that are arranged in one column and that are respectively connected to each control gate electrode of the memory cells constituting each of the series circuit unit. A voltage by which the selected non-volatile transistor works in a saturation state is applied to the control gate electrode of the selected transistor of a series circuit unit by a column line, thereby injecting hot electrons from the semiconductor substrate into the floating gate electrode.

Abstract: A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.

Abstract: A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.

Abstract: A nonvolatile memory includes paired memory elements each including a storage transistor having a control gate and a floating gate. Through a write operation, one of the storage transistors is brought into a depletion state and the other storage transistor is brought into an enhancement state. Subsequently, a connection transistor is operated in order to serially connect the paired memory elements. As result, a binary signal corresponding to the statuses of the paired storage transistors is outputted.

Abstract: According to one embodiment, a nonvolatile storage circuit (100) can include a volatile portion (102) that includes p-channel metal-oxide-semiconductor (MOS) transistors (106-0 and 106-1) and n-channel MOS (NMOS) transistors (108-0 and 108-1) arranged in a complementary MOS (CMOS) latch configuration. Also included are nonvolatile devices (116-0 and 116-1) disposed between PMOS transistor 106-0 and NMOS transistor 108-0, and between PMOS transistor 106-1 and NMOS transistor 108-1. Nonvolatile devices (116-0 and 116-1) can include silicon-oxide-nitride-semiconductor (SONOS) transistors that can be programmed to opposite states to recall a logic value when power is applied to the nonvolatile storage circuit (100). In a read mode, a bias voltage VBIAS can be applied to nonvolatile devices (116-0 and 116-1) that tends to retain charge in both nonvolatile devices (116-0 and 116-1).