Sensing Circuitry (e.g., Current Mirror) Patents (Class 365/185.21)
  • Patent number: 10388384
    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 10388350
    Abstract: A memory system has a nonvolatile memory having a plurality of readable and writable memory cells, a write voltage control unit that controls at least one of a voltage value and a pulse width of a write voltage of the nonvolatile memory in accordance with a weight of a signal processing path or a signal processing node, a write unit that writes data in two or more memory cell groups among the plurality of memory cells using the write voltage controlled by the write voltage control unit, a reversal probability detection unit that detects a reversal probability of the memory cell group when writing data is written by the write unit, and a weight conversion unit that converts the detected reversal probability into a weight.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Yousuke Isowaki, Michael Arnaud Quinsat, Kenichiro Yamada, Kosuke Tatsumura
  • Patent number: 10366729
    Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Tai-Yuan Tseng, Anirudh Amarnath
  • Patent number: 10366760
    Abstract: The present application provides a NAND flash memory with wordline voltage compensate, including wordlines. Each wordline corresponds to a wordline voltage with a compensated temperature coefficient. The wordlines are divided into a plurality of groups, each group corresponds to a compensated temperature coefficient. Each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses, or divided by zones having fixed number of wordlines.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: July 30, 2019
    Assignees: GigaDevice Semiconductor (Shanghai) Inc., GigaDevice Semiconductor (Beijing) Inc., GigaDevice Semiconductor (Hefei) Inc.
    Inventor: Minyi Chen
  • Patent number: 10347348
    Abstract: The invention provides a semiconductor memory device capable of setting input data correctly, including: an input circuit outputting input data to a data bus; a logic circuit outputting the input data on the data bus to digit lines selected by a column address in response to a writing clock signal synchronized with an external clock signal; a page buffer holding data of the digit lines in holding circuits of a column selected by the column address in response to an inner clock signal generated by delaying the writing clock signal, and an address counter generating the column address in response to the writing clock signal. The column address is supplied to the logic circuit in response to the writing clock signal, and the column address is supplied to the page buffer in response to the inner clock signal which has been delayed.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 9, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Hidemitsu Kojima
  • Patent number: 10339513
    Abstract: Technologies for closed-looped testing of integrated circuit card payment terminals include loading a test profile onto an integrated circuit payment card. Authorization request and response messages are locally generated and translated to simulate acquirer processor processing and payment network processing. An outcome report indicative of the outcome of the test transaction is generated and transmitted to a remote certification server. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: July 2, 2019
    Assignee: Worldpay, LLC
    Inventors: Patricia Lynn Walters, Steven Scott Cole
  • Patent number: 10340004
    Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Cheng Chou
  • Patent number: 10297327
    Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 21, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 10290343
    Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: ChaeHoon Kim, Kyoman Kang, Tae-Hong Kwon, Taeyun Lee, Jin-Young Chun
  • Patent number: 10289313
    Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Han Liu, Shantanu R. Rajwade, Pranav Kalavade
  • Patent number: 10217496
    Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 26, 2019
    Assignee: ARM Limited
    Inventors: Vivek Nautiyal, Jitendra Dasani, Satinderjit Singh, Shri Sagar Dwivedi, Bo Zheng, Fakhruddin Ali Bohra
  • Patent number: 10210924
    Abstract: A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihiko Kamata
  • Patent number: 10199112
    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong
  • Patent number: 10192618
    Abstract: An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Soo Pyo, Hyuntaek Jung, Taejoong Song, Boyoung Seo
  • Patent number: 10165210
    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges accumulated in the photodiode to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a SF gate terminal and provide an amplified signal to a source follower source terminal. A row select transistor is coupled to receive the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor controlled by a bitline enable voltage is coupled to link between the bitline and a bitline source node. The bitline is coupled to an idle voltage generator, a blacksun voltage generator, and a clamp voltage generator.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 25, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rui Wang, Hiroaki Ebihara
  • Patent number: 10134346
    Abstract: A display driving circuit includes a storage module, a switch module and a current detection module. The storage module is configured to store a control program of inversion driving modes for liquid crystal and output to the switch module an inversion drive signal corresponding to different inversion driving modes for liquid crystal. The current detection module is configured to detect a change in current and output a current detection signal corresponding to the switch module based on a magnitude of the detected current value. The switch module is configured to determine a desired inversion driving mode for liquid crystal based on the current detection signal and output an inversion driving signal corresponding to the desired inversion driving mode for liquid crystal.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 20, 2018
    Assignee: BOE Technology Group Co., Ltd
    Inventor: Zhicheng Wang
  • Patent number: 10134481
    Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini
  • Patent number: 10127988
    Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park, Erwin E. Yu
  • Patent number: 10115469
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Patent number: 10115462
    Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Salvatore Polizzi, Maurizio Francesco Perroni
  • Patent number: 10109351
    Abstract: A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Patent number: 10109350
    Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 23, 2018
    Assignee: AP Memory Corp., USA
    Inventor: Wenliang Chen
  • Patent number: 10055286
    Abstract: A data storage device includes a nonvolatile memory device including a target memory region; and a controller suitable for performing a read operation by reading a data chunk from the target memory region based on a read bias and performing an error correction operation for the data chunk, iterating the read operation according to a result of the error correction operation, and adjusting the read bias based on at least one read bias used in one or more previous read operations and at least one correction failure index corresponding to the at least one read bias.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 21, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Kim
  • Patent number: 10043555
    Abstract: Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 7, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kobi Danon, Yoram Betser, Alex Kushnarenko
  • Patent number: 10032489
    Abstract: This disclosure provides a method and apparatus for detecting a transition of a memory cell current from a first state to a second state. An example apparatus includes a memory cell, a supplemental current source, a comparator, a reference voltage and a reference current source in a configuration that allows for real time detection of the transition of a memory cell. Detection of a memory cell current transition is captured when the output of the comparator transitions from one state to a second state in response to a sensing voltage exceeding the reference voltage.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 24, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yingchang Chen, Xiaoxia Wu
  • Patent number: 10031686
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 24, 2018
    Assignee: Unity Semiconductor Corporation
    Inventor: Chang Hua Siau
  • Patent number: 10026473
    Abstract: A non-volatile memory device for selectively performing a recovery operation and a method of operating the same are provided. The method of operating a non-volatile memory device includes receiving a first read command, performing a first sensing operation in response to the first read command, and receiving a second read command. The method further includes completing a memory operation corresponding to the first read command without performing a recovery operation when the second read command is received before the first sensing operation is completed, and performing a second sensing operation in response to the second read command.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jun Yoon, Jae-Woo Im
  • Patent number: 10020311
    Abstract: A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 10, 2018
    Assignee: AP MEMORY TECHNOLOGY CORPORATION
    Inventors: Owen Li, Wenliang Chen
  • Patent number: 10014052
    Abstract: Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 3, 2018
    Assignee: ARM Ltd.
    Inventor: Bal S. Sandhu
  • Patent number: 10008276
    Abstract: Techniques are presented for determining current leakage from a memory array or other circuit based on a low voltage path. For example, the technique can be applied to determine word line to word line leakage. By looking at a count for the clock used in regulating the low voltage output node, the amount of leakage can be determined. The leakage determination can be performed as part of test process or during normal memory operations.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 26, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jonathan Huynh, Jongmin Park
  • Patent number: 9997247
    Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 12, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Akira Goda
  • Patent number: 9990977
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 5, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christopher John Kawamura
  • Patent number: 9972366
    Abstract: A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 15, 2018
    Assignee: SK hynix Inc.
    Inventor: Seok Joon Kang
  • Patent number: 9960672
    Abstract: A high voltage generator includes a voltage converting device that increases a level of an input voltage and outputs an output voltage having a level higher than the level of the input voltage. The high voltage generator further includes a precharge controller that gradually increases the level of the input voltage up to a level of an external voltage based on a reference voltage and the output voltage.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: May 1, 2018
    Assignees: SK HYNIX INC., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Young-Il Kim, Sang-Sun Lee, Sung-Wook Choi
  • Patent number: 9947390
    Abstract: The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory cell arrays are the same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays. The data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays. The data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are the same.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 17, 2018
    Assignees: TSINGHUA UNIVERSITY, GRADUATE SCHOOL AT SHENZHEN, TSINGHUA UNIVERSITY
    Inventors: Liyang Pan, Xinhong Hong, Dong Wu
  • Patent number: 9922706
    Abstract: A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: March 20, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu
  • Patent number: 9892769
    Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 13, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Chuntian Yu, Xiaoyan Liu
  • Patent number: 9859000
    Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 2, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Seow-Fong Lim, Koying Huang
  • Patent number: 9858987
    Abstract: A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limied
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh
  • Patent number: 9852784
    Abstract: A bit line clamp voltage generator circuit for a Spin Torque Transfer Magnetoresistive Random Access Memory is provided. The circuit includes a negative channel Field Effects Transistor having a source, a drain, and a gate, the gate being connected to the drain. The circuit further includes a resistor Rs having a first end connected to a first voltage and a second end connected to the source. The circuit also includes a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventor: John K. DeBrosse
  • Patent number: 9837149
    Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 5, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Bruce Lynn Bateman, Christophe Chevallier, Darrell Rinerson, Chang Hua Siau
  • Patent number: 9805812
    Abstract: An operating method of a storage device which includes a nonvolatile memory is provided. The operating method includes performing a first program operation on selected memory cells of the nonvolatile memory and storing a first time when the first program operation is performed; and adjusting a program parameter according to a difference between the first time and a second time, and performing a second program operation on the selected memory cells using the adjusted program parameter, the second time being a time when the second program operation is performed.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Donghun Kwak
  • Patent number: 9805796
    Abstract: A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 31, 2017
    Assignee: Copee Technology Company
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Patent number: 9792982
    Abstract: Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 17, 2017
    Assignee: ARM Ltd.
    Inventor: Bal S. Sandhu
  • Patent number: 9786378
    Abstract: A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 10, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Liang Pang, Caifu Zeng, Xuehong Yu, Yingda Dong
  • Patent number: 9773529
    Abstract: A method for operating a read command of N complementary memory cells, the method includes the steps of determining if each of the first and second memory cells of the N complementary memory cells is in a first binary state or a second binary state, generating a count value by counting a total number of the first and second memory cells that are in the first binary state, and determining if the N complementary memory cells are programmed or erased based on a result of comparing the count value to a threshold number.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 26, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kobi Danon, Yoram Betser, Alex Kushnarenko
  • Patent number: 9761316
    Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 12, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Victorien Brecte
  • Patent number: 9748274
    Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 29, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka, Tatsuya Onuki, Yutaka Shionoiri, Naoaki Tsutsui, Shunpei Yamazaki
  • Patent number: 9748479
    Abstract: A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 29, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Juan P. Saenz, Christopher J. Petti
  • Patent number: RE46556
    Abstract: A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien Chun Yang, Chih-Chang Lin, Ming-Chieh Huang