Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell and a memory cell connected to a word line, a first bit line BL connected to the memory cell, a second bit line BL connected to the memory cell, and a control circuit. The control circuit includes a first transistor provided between the first bit line and the node and including one end electrically connected to the node, and a second transistor provided between the second bit line and the node and including one end electrically connected to the node; the second transistor is provided adjacent to the first transistor; and the control circuit is configured to set one of the first transistor and the second transistor in an ON state while setting the other in an OFF state.

Abstract: Systems, devices, and methods for charging a node of a sense component during an access operation are described. The node of the sense component may be coupled with a charge transfer device and with a voltage source using a switching component. The voltage source may be configured to output different voltages (e.g., two different precharge voltages) during different phases of the access operation. The switching component may be configured to selectively couple the node with the voltage source and the different voltages may be used to precharge the node during different phases of the access operation. The different voltages of the voltage source may provide an adequate sense window.

Abstract: Apparatus and methods are disclosed for providing a bias. A main diode has first and second terminals that connect to a high voltage (HV) line and to an HV regulated line, respectively. The main diode provides a voltage on the HV regulated line lower than a voltage of the HV line. A first current mirror provides a first current. The current mirror connects to the first terminal of the main diode and the HV regulated line. A second current mirror provides a second current. The second current mirror connects to the HV line, the first current mirror, and a low-voltage (LV) line. An impedance is between the LV line and the HV regulated line. A voltage differential between the HV regulated line and the LV line below a low-voltage threshold, and a voltage differential between the HV regulated line and the HV line above the low-voltage threshold are provided.

Abstract: A memory system includes a host interface, a nonvolatile memory, a power supply circuit, a protection circuit, and a first voltage monitor circuit. The power supply circuit is between the host interface and the nonvolatile memory, and supplies primary power to the nonvolatile memory. The protection circuit is between the host interface and the power supply circuit, and configured to clamp a power supply signal supplied from the host interface to the power supply circuit to a first voltage. The first voltage monitor circuit is between the host interface and the protection circuit, and configured to monitor a voltage level of the power supply signal supplied from the host interface and cause the voltage level of the power supply signal supplied to the power supply circuit to be decreased from the first voltage to a second voltage when the monitored voltage level is below a first threshold voltage.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.

Abstract: A sensing circuit with adaptive local reference generation of a resistive memory is configured to adaptively sense a first bit line current of a first bit line and a second bit line current of a second bit line via one sense amplifier. The sense amplifier has a first output node and a second output node. The adaptive local reference generator is electrically connected to the sense amplifier and generating a reference current equal to a sum of the second bit line current and a local reference current. A first bit line current flows through the first output node during a first bit line time interval. A second bit line current flows through the first output node during a second bit line time interval. The first bit line time interval is different from the second bit line time interval.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: A time-based sensing circuit to convert resistance of a programmable resistive element into logic states is disclosed. A programmable resistive memory has a plurality of programmable resistive devices. At least one of the programmable resistive devices can have at least one programmable resistive element (PRE) that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the PRE resistance into a logic state.

Abstract: A physical unclonable function (PUF) circuit generates one or more bit values. The PUF circuit includes a first one-time programmable (OTP) memory cell, a second OTP memory cell, and a latch circuit connected to the first and second OTP memory cells. The latch circuit initiates programming of the first and second OTP memory cells, detects a faster programming OTP memory cell of the first and second OTP memory cells, inhibits programming of a slower programming OTP memory cell of the first and second OTP memory cells, and stores a first bit value when the first OTP memory cell is the faster programming OTP memory cell and a second bit value when the second OTP memory cell is the faster programming OTP memory cell.

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

Abstract: A method of training artificial intelligence to estimate sensing voltages for a storage device is provided, which includes steps of: supplying initial sensing voltages to memory units; defining various storing states; comparing threshold voltages of the memory units with the initial sensing voltages to classify the memory units; calculating a ratio of the number of the memory units in a strong correct region to the number of in the strong correct region and a weak correct region; calculating a ratio of the number of the memory units in a strong error region to the number of in the strong error region and a weak error region; calculating the number of the memory units in the weak correct and error regions to obtain a histogram parameter; inputting the ratios and parameter to an artificial intelligence neural network; and using machine learning to analyze practical sensing voltages.

Abstract: A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.

Abstract: A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.

Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.

Abstract: A digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and is configured to be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node is configured to be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node and to transform between high electrical potentials on the first node and lower electrical potentials on the third node while the second digital unit communicates with the first digital unit.

Abstract: The technology disclosed in this patent document can be implemented in embodiments to provide a memory system capable of improving a read operation, using an error correction technique (e.g., chipkill) that recovers data in correcting a data failure including a multibit failure, and an operation method of the memory system. The disclosed read operations based on recovery can be used for retrieving data from a memory chip by reconstructing the same data from other memory chips without accessing the memory chip and can be applied in various memory systems.

Abstract: A memory device comprises a memory array and a memory control unit. The memory includes multi-level memory cells. The memory control unit is configured to: initiate programming of memory cells of the memory array using a first pass programming operation, wherein the first pass programming operation places programming data using a first and second voltage threshold distributions; read programmed memory cells using a first read voltage level on word lines of the memory cells; read the programmed memory cells using a second read voltage level on the word lines of the memory cells; determine a number of the programmed memory cells with a voltage threshold placed between the first and second voltage threshold distributions by the programming; and suspend second pass programming of the memory cells in response to the determined number of cells exceeding a specified threshold number, and initiate a second pass programming operation otherwise.

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

Abstract: A memory system includes a nonvolatile semiconductor memory including memory cells storing data, and a controller configured to control a read operation of the nonvolatile semiconductor memory to read data from the nonvolatile semiconductor memory. The controller is configured to determine a read voltage to be used for reading data from the nonvolatile semiconductor memory depending on whether the read operation is performed during a first period after an end of a write operation of the data or during a second period following the first period, upon determining that the read operation is performed during the first period, change the read voltage in accordance with an elapsed time after the end of the write operation of the data, and upon determining that the read operation is performed during the second period, determine the read voltage regardless of the elapsed time after the end of the write operation of the data.

Abstract: A method for detecting storing states of a solid state storage device is provided, including steps of: applying sensing voltages to memory units; comparing threshold voltages of the memory units with the sensing voltages and accordingly to define the storing states including a strong correct region, a weak correct region, a strong error region and a weak error region, in which the memory units are classified; calculating the number of the memory units in the storing states; calculating a strong correct ratio of the number of the memory units in the strong correct region to the number of the memory units in the strong and weak correct regions; calculating a strong error ratio of the number of the memory units in the strong error region to the number of the memory units in the strong and weak error regions; and generating a log-likelihood ratio based on said ratios.

Abstract: A nonvolatile memory device includes: a plurality of first reference cells that are connected in parallel, and are in an intermediate state between an erased state and a programmed state; a first current mirror circuit that generates a first mirror current proportional to a sum of currents flowing through the plurality of first reference cells in a state in which the plurality of first reference cells are selected; and a sense amplifier that, in a readout mode, generates a reference current based on at least the first mirror current, and reads out data stored in a memory cell by comparing a current flowing through the memory cell with the reference current.

Abstract: According to one embodiment, a semiconductor storage device includes a first plane having a first plurality of memory cells, a second plane having a second plurality of memory cells, first bit lines which are connected to the first plane, second bit lines which are connected to the second plane, a plurality of first sense amplifiers which charge the plurality of first bit lines, and a plurality of second sense amplifiers which charge the plurality of second bit lines. When the first and second planes operate in parallel, a total sum of currents supplied to the plurality of first bit lines from the plurality of first sense amplifiers and currents supplied to the plurality of second bit lines from the plurality of second sense amplifiers reaches a first current value, then decreases to a second current value, and then increases to a third current value.

Abstract: Methods of operating a memory including applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining an expected data age of the plurality of memory cells in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

Abstract: Apparatus and methods are disclosed for providing a bias. A main diode has first and second terminals that connect to a high voltage (HV) line and to an HV regulated line, respectively. The main diode provides a voltage on the HV regulated line lower than a voltage of the HV line. A first current mirror provides a first current. The current mirror connects to the first terminal of the main diode and the HV regulated line. A second current mirror provides a second current. The second current mirror connects to the HV line, the first current mirror, and a low-voltage (LV) line. An impedance is between the LV line and the HV regulated line. A voltage differential between the HV regulated line and the LV line below a low-voltage threshold, and a voltage differential between the HV regulated line and the HV line above the low-voltage threshold are provided.

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.

Abstract: A reference current circuit usable in a memory circuit has an input leg comprising a current sink and a first resistor connected between the current sink and a voltage supply node, and has an output leg connected between the supply voltage node and a load. The output leg includes a second resistor and a control transistor. The load is connected in current flow communication with the control transistor. An amplifier has a first input connected to the output node of the current sink in the input leg and a second input connected to the second resistor. An output of the amplifier is connected to the gate of the control transistor.

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. The selected and unselected sense circuits are configured to perform a state-dependent pre-charge operation during the sense operation. In particular, the selected sense circuits may enable respective pre-charge circuit paths that supply a pre-charge supply voltage to respective sense nodes in the selected sense circuits. Additionally, the unselected sense circuits may disable respective pre-charge circuit paths to prevent the supply of the pre-charge supply voltage to respective sense nodes in the unselected sense circuits. A sense circuit controller may control latches to control the enabling and disabling of the pre-charge circuit paths.

Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: A redundant circuit for a SRAM device is provided. The redundant circuit includes: a pair of a first transistor and a second transistor, connected between a power source voltage and a power source terminal of each of the input/output memory units, wherein the pair of the first transistor and the second transistor are connected in parallel with each other, and the first transistor has a greater mutual conductance than the second transistor; and a redundancy control circuit configured to detect a voltage of the power source terminal of each of the input/output memory units when the first transistor is turned off and the second transistor is turned on. When the detected voltage of the power source terminal is decreased by a predetermined value or more from a predetermined reference voltage, the input/output memory unit is determined in a defective state, and the input/output memory unit in the defective state is redundantly replaced with a normal input/output memory unit.

Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.

Abstract: A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.

Abstract: A current-sensing circuit for a memory and a sensing method thereof are provided. The current-sensing circuit includes a pre-charge circuit, a sensing current-to-voltage generator, an auxiliary current-to-voltage generator, a reference current-to-voltage generator, and a detection circuit. The pre-charge circuit provides a pre-charge signal to a selected bit line during a pre-charge time period. The sensing current-to-voltage generator generates a sensing voltage to a memory cell current of the selected bit line via a first load. The auxiliary current-to-voltage generator provides a detection voltage to a portion of the memory cell current of the selected bit line via a second load. The reference current-to-voltage generator provides a reference voltage during a data-sensing time period. The detection circuit determines an end time point of the pre-charge time period by comparing a detected voltage generated by the second load with a reference voltage.

Abstract: A memory system has a nonvolatile memory having a plurality of readable and writable memory cells, a write voltage control unit that controls at least one of a voltage value and a pulse width of a write voltage of the nonvolatile memory in accordance with a weight of a signal processing path or a signal processing node, a write unit that writes data in two or more memory cell groups among the plurality of memory cells using the write voltage controlled by the write voltage control unit, a reversal probability detection unit that detects a reversal probability of the memory cell group when writing data is written by the write unit, and a weight conversion unit that converts the detected reversal probability into a weight.

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.

Abstract: The present application provides a NAND flash memory with wordline voltage compensate, including wordlines. Each wordline corresponds to a wordline voltage with a compensated temperature coefficient. The wordlines are divided into a plurality of groups, each group corresponds to a compensated temperature coefficient. Each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses, or divided by zones having fixed number of wordlines.

Abstract: The invention provides a semiconductor memory device capable of setting input data correctly, including: an input circuit outputting input data to a data bus; a logic circuit outputting the input data on the data bus to digit lines selected by a column address in response to a writing clock signal synchronized with an external clock signal; a page buffer holding data of the digit lines in holding circuits of a column selected by the column address in response to an inner clock signal generated by delaying the writing clock signal, and an address counter generating the column address in response to the writing clock signal. The column address is supplied to the logic circuit in response to the writing clock signal, and the column address is supplied to the page buffer in response to the inner clock signal which has been delayed.

Abstract: Technologies for closed-looped testing of integrated circuit card payment terminals include loading a test profile onto an integrated circuit payment card. Authorization request and response messages are locally generated and translated to simulate acquirer processor processing and payment network processing. An outcome report indicative of the outcome of the test transaction is generated and transmitted to a remote certification server. Other embodiments are described and claimed.

Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.

Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.