Reference Signal (e.g., Dummy Cell) Patents (Class 365/185.2)
  • Patent number: 10896703
    Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Vijayakrishna J. Vankayala
  • Patent number: 10878909
    Abstract: A semiconductor device includes: a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors; one or more dummy word lines coupled to the one or more dummy transistors; and a plurality of select lines respectively coupled to the plurality of select transistors. When a program voltage is applied to a selected dummy word line among the one or more dummy word lines, a first dummy word line voltage may be applied to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Un Sang Lee
  • Patent number: 10861564
    Abstract: A memory circuit and a data bit status detector thereof are provided. The data bit status detector includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sense amplifying circuit has a first sense input end and a second sense input end. The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides the first impedance between the first sense input end and a reference grounding end according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides the second impedance between the second sense input end and the reference grounding end according to the bias voltages.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 8, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Zhe-Yi Lin, Wen-Chiao Ho
  • Patent number: 10777286
    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
  • Patent number: 10770125
    Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Adam D. Johnson
  • Patent number: 10762964
    Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10733047
    Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Mostafa El Gamal, Jim Fitzpatrick
  • Patent number: 10734056
    Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: El Mehdi Boujamaa, Cyrille Nicolas Dray
  • Patent number: 10714185
    Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Umberto Di Vincenzo
  • Patent number: 10706897
    Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chandra C. Varanasi
  • Patent number: 10685702
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Patent number: 10672478
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 10650901
    Abstract: An electronic device includes a controller, a non-transitory computer-readable storage medium including memory cells having a plurality of threshold voltage distributions and storing operation codes executable by the controller.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Nam Yoo
  • Patent number: 10636496
    Abstract: A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Ching Li, Yi-Ching Liu
  • Patent number: 10629247
    Abstract: Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 21, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Salil Kale, Shreejith Kv, Aneesh Puthoor, Gopu S, Narayan K
  • Patent number: 10580500
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Jae Hyuk Bang
  • Patent number: 10580485
    Abstract: Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions. The method also includes determining a bias value based on the selected bias function and the wordline. The method also includes adjusting a read level in the non-volatile memory based on the bias value. The method also includes performing the memory access operation on the wordline of the non-volatile memory using the adjusted read level. The bias functions may be linear functions and adjusted in response to detecting a recalibration condition.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Alexander Bazarsky, Tomer Tzvi Eliash, David Rozman, Eran Sharon, Arthur Shulkin
  • Patent number: 10566068
    Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoji Kashihara
  • Patent number: 10553293
    Abstract: A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 4, 2020
    Inventor: Fu-Chang Hsu
  • Patent number: 10490270
    Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: James S Ignowski, Martin Foltin, Yoocharn Jeon
  • Patent number: 10482973
    Abstract: A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yun Lee, Joon Soo Kwon, Byung Soo Kim, Sang-Soo Park, Il Han Park, Jong-Hoon Lee
  • Patent number: 10460810
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 29, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 10446202
    Abstract: Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of configuration memory of a second group of sectors of the programmable logic device. The memory reads of the configuration memory of the second group of sectors start at a second start time within the first memory read period. The second start time is different from the first start time. By offsetting the start times of memory reads, power distribution noise may be reduced.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 15, 2019
    Assignee: Altera Corporation
    Inventor: Sean R. Atsatt
  • Patent number: 10438668
    Abstract: A power supply management device includes a first input terminal that receives an input voltage, and a first power supply circuit that outputs a voltage obtained by converting the input voltage. The first power supply circuit further outputs a first voltage responsive to a first signal being received by the first input terminal. The first power supply circuit yet further outputs a second voltage responsive to a second signal different from the first signal being received by the first input terminal.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Wataru Okamoto
  • Patent number: 10418097
    Abstract: Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Avraham, Eran Sharon, Ran Zamir, Alexander Bazarsky
  • Patent number: 10381062
    Abstract: A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 13, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Takashi Yamada
  • Patent number: 10366736
    Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 30, 2019
    Assignee: Synopsys, Inc.
    Inventors: Colin Stewart Bill, Harry Luan
  • Patent number: 10366765
    Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
  • Patent number: 10339996
    Abstract: Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on Erase-Write (EW) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Jung Hwan Lee
  • Patent number: 10340012
    Abstract: Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Jung Hwan Lee
  • Patent number: 10340009
    Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10319448
    Abstract: A reference-current generation method for flash includes first and second memory arrays separated by a word-line switching circuit. A reference-current generation circuit includes rows of reference cells, the first row parallel with the other rows of the first memory array and having the same number of columns as the other rows thereof, and the second row parallel with the other rows of the second memory array and having the same number of columns as the other rows thereof. The first reference word line of the first row is disconnected with the second reference word line of the second row. After programming, the first row enables the first memory array to create the first reference current used while performing read operation for the second memory array, and the second row enables the second memory array to create the second reference current used while performing read operation for the first memory array.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Guangjun Yang
  • Patent number: 10283206
    Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 7, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen, Vipin Tiwari
  • Patent number: 10276256
    Abstract: A device may include a first analog memory device to sample an analog input during a first time window of a sampling window, store a first analog signal based on sampling the analog input, and provide a first analog output after storing the first analog signal. The device may include a second analog memory device to sample the analog input during a second time window of the sampling window, store a second analog signal based on sampling the analog input, and provide a second analog output after storing the second analog signal. An output rate may be different from a sampling rate associated with sampling the analog input. An output order may be different from a sampling order associated with sampling the analog input. A time at which a read-out phase is performed, may be significantly different from a time at which a write phase is performed.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Marcus Edward Hennecke, Franz Michael Darrer
  • Patent number: 10248484
    Abstract: An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined functions. The logic circuits configured by the CRAM sectors may vary in their criticality to the operation of the integrated circuit. A prioritized error detection schedule may be provided to error detection circuitry, allowing a more frequent check of sectors that are used to configure logical circuitry that is critical to the operation of the integrated circuit. Upon detecting an error in a given CRAM sector, a sensitivity map may be used to determine the logical location corresponding to the errant CRAM sector. A sensitivity processor may assign a criticality level to the logical location, and appropriate corrective action for the errant CRAM sector may be determined based on the criticality level and the logical location corresponding to the sector.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Michael David Hutton, Sean R. Atsatt
  • Patent number: 10249373
    Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Campardo, Salvatore Polizzi
  • Patent number: 10216965
    Abstract: This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 26, 2019
    Assignee: STC.UNM
    Inventors: James Plusquellic, Swarup Bhunia
  • Patent number: 10204675
    Abstract: A semiconductor memory apparatus of the technology includes a current sink circuit configured to allow a portion of a current flowing through a memory cell to flow to a negative voltage terminal in a read operation and a sense amplifier configured to detect data of the memory cell and a detection result in response to a sense amplifier enable signal in the read operation. The current sink circuit varies an amount of the current flowing to the negative voltage terminal in response to the sense amplifier enable signal.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Sang Hoon Jeong
  • Patent number: 10199093
    Abstract: A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 5, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Sang Nguyen, Hagop Nazarian, Tianhong Yan
  • Patent number: 10186320
    Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Marc Battista, Victorien Brecte
  • Patent number: 10181350
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 15, 2019
    Assignee: Arm Limited
    Inventors: Shidhartha Das, Andreas Hansson, Akshay Kumar, Piyush Agarwal, Azeez Jennudin Bhavnagarwala, Lucian Shifren
  • Patent number: 10180876
    Abstract: A memory controller includes: a host interface configured to receive a read command from the outside of the memory controller; and a read controller configured to perform a data read operation on a memory device according to the read command. The read controller performs a data read operation on a set of memory cells and determines a first and second values. The first value is a number of memory cells having a first threshold voltage among the set of memory cells, and the second value is a number of memory cells having a second threshold voltage among the set of memory cells. The read controller determines a first read voltage based on only the first and second values and performs a data read operation on the set of memory cells using the first read voltage.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tokumasa Hara
  • Patent number: 10147487
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Patent number: 10121521
    Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Chandra C. Varanasi
  • Patent number: 10121553
    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 6, 2018
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 10115467
    Abstract: A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 30, 2018
    Assignee: Jonker LLC
    Inventors: David K. Y. Liu, John Nicholas Gross
  • Patent number: 10096367
    Abstract: A power supply circuit and a semiconductor storage device that can achieve low power consumption of the power supply circuit that includes a charge pump circuit are provided. The semiconductor storage device includes a charge pump unit which generates and outputs a boosted voltage by boosting a source voltage, a voltage monitoring unit that performs comparison and determination on magnitudes of a divided voltage obtained by dividing the boosted voltage and a predetermined reference voltage, a charge pump control unit that causes the charge pump unit to operate when the divided voltage is equal to or lower than the reference voltage and causes the charge pump unit to stop when the divided voltage is higher than the reference voltage based on a result of the comparison and determination, and a voltage monitoring control unit that causes the voltage monitoring unit to intermittently stop.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: October 9, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyuki Tanikawa
  • Patent number: 10097184
    Abstract: One example discloses A differential receiver, including: a set of high voltage differential inputs configured to receive a first range of differential voltages; a first level shifter configured to generate a second range of differential voltages that are less than the first range of differential voltages; and a first low voltage differential comparator coupled to the first level shifter and configured to generate a first differential receiver output based on the second range of differential voltages.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 9, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xiaowen Wu, Lei Tian, Yongqin Liang
  • Patent number: 10095574
    Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 10049760
    Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shiino, Tomoaki Nakano, Shigefumi Irieda, Masashi Yoshida