Reference Signal (e.g., Dummy Cell) Patents (Class 365/185.2)
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Patent number: 12154656Abstract: A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.Type: GrantFiled: June 30, 2022Date of Patent: November 26, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
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Patent number: 12147666Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.Type: GrantFiled: November 3, 2022Date of Patent: November 19, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yohan Lee, Jaeduk Yu, Jiho Cho
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Patent number: 12087362Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.Type: GrantFiled: March 23, 2022Date of Patent: September 10, 2024Assignee: KIOXIA CORPORATIONInventors: Avi Steiner, Kenji Sakurada, Eyal Nitzan, Yasuhiko Kurosawa
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Patent number: 12073875Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.Type: GrantFiled: September 13, 2022Date of Patent: August 27, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunsub Rie, Eunseok Shin, Youngdon Choi, Changsoo Yoon, Hyunyoon Cho, Junghwan Choi
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Patent number: 12051467Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.Type: GrantFiled: June 4, 2020Date of Patent: July 30, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Huai-Yuan Tseng, Henry Chin, Deepanshu Dutta
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Patent number: 11978528Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.Type: GrantFiled: January 28, 2022Date of Patent: May 7, 2024Assignee: Infineon Technologies LLCInventors: Shivananda Shetty, Yoram Betser, Pawan Singh, Stefano Amato, Alexander Kushnarenko
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Patent number: 11972823Abstract: A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.Type: GrantFiled: September 11, 2022Date of Patent: April 30, 2024Assignee: APPLE INC.Inventor: Assaf Shappir
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Patent number: 11923036Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.Type: GrantFiled: February 13, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Patent number: 11862242Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.Type: GrantFiled: March 9, 2022Date of Patent: January 2, 2024Assignee: Lodestar Licensing Group LLCInventor: Dmitri Yudanov
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Patent number: 11862233Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).Type: GrantFiled: May 19, 2022Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Dong Liu, Tianhao Diwu, Xikun Chu
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Patent number: 11822428Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.Type: GrantFiled: November 21, 2022Date of Patent: November 21, 2023Assignee: Silicon Motion, Inc.Inventor: Tsung-Chieh Yang
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Patent number: 11735270Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.Type: GrantFiled: July 16, 2020Date of Patent: August 22, 2023Assignee: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
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Patent number: 11735271Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells, and a peripheral circuit configured to perform a read operation and a dummy read operation on the memory block. A discharge slope of a pass voltage applied to the memory block during the read operation is greater than a discharge slope of a dummy pass voltage applied to the memory block during the dummy read operation.Type: GrantFiled: July 9, 2021Date of Patent: August 22, 2023Assignee: SK hynix Inc.Inventors: Jong Wook Kim, Noh Yong Park
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Patent number: 11688464Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory cells and a memory controller. The memory controller may be configured to control the memory device to generate dummy data based on write data, when a size of the write data is less than a preset size, and to store program data including the write data and the dummy data in selected memory cells among the plurality of memory cells.Type: GrantFiled: April 5, 2021Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventor: Beom Rae Jeong
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Patent number: 11670384Abstract: A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.Type: GrantFiled: January 28, 2022Date of Patent: June 6, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Weirong Chen, Qiang Tang
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Patent number: 11659297Abstract: An image sensor includes a plurality of image sensor cells, each configured to generate or not generate an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes a plurality of charge pump cells selectably sourcing charge to the first power supply node in response to one of multiple enable signals, and a charge pump cell quantity controller circuit generating the enable signals. Each enable signal is either in an active or inactive state, and each charge pump cell sources charge to the first power supply node in response to receiving an enable signal in an active state.Type: GrantFiled: October 27, 2020Date of Patent: May 23, 2023Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Chao Yang, Dazhi Wei, Mohamed Elsayed
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Patent number: 11657880Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors.Type: GrantFiled: July 11, 2022Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Shuji Tanaka, Masashi Yoshida, Masanobu Saito, Yoshihiko Kamata
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Patent number: 11631451Abstract: A semiconductor memory training method includes: selecting two adjacent reference voltages from a plurality of reference voltages as a first reference voltage and a second reference voltage; obtaining a first minimum margin value for the plurality of target signal lines under the first reference voltage; obtaining a second minimum margin value for the plurality of target signal lines under the second reference voltage, according to a minimum margin value for each target signal line under the second reference voltage; determining a target interval for an expected margin value according to the first minimum margin value and the second minimum margin value, the expected margin value being the maximum one among the minimum margin values for the plurality of target signal lines under the plurality of reference voltages; and searching for the expected margin value in the target interval.Type: GrantFiled: March 9, 2021Date of Patent: April 18, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangteng Long, Xiaofeng Xu, Junwei Lian
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Patent number: 11621043Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: June 25, 2021Date of Patent: April 4, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
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Patent number: 11581027Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.Type: GrantFiled: December 6, 2021Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Patent number: 11568941Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.Type: GrantFiled: September 10, 2021Date of Patent: January 31, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Patent number: 11546177Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.Type: GrantFiled: February 7, 2020Date of Patent: January 3, 2023Assignee: STMicroelectronics (Rousset) SASInventor: Francesco La Rosa
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Patent number: 11537469Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.Type: GrantFiled: September 8, 2021Date of Patent: December 27, 2022Assignee: Silicon Motion, Inc.Inventor: Tsung-Chieh Yang
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Patent number: 11527279Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.Type: GrantFiled: June 22, 2020Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
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Patent number: 11488682Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.Type: GrantFiled: June 24, 2020Date of Patent: November 1, 2022Assignee: SanDisk Technologies LLCInventors: Tomer Eliash, Alexander Bazarsky, Eran Sharon
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Patent number: 11468956Abstract: The present disclosure relates to a memory device that includes a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, which includes a plurality of program loops each including an operation of applying a program voltage to a selected word line commonly connected to the plurality of memory cells and a verify operation of applying at least one verify voltage among verify voltages respectively corresponding to target program states of the plurality of memory cells. The memory device additionally includes control logic configured to control the peripheral circuit so that the at least one verify voltage increases according to a program loop of the plurality of program loops during the program operation.Type: GrantFiled: November 20, 2020Date of Patent: October 11, 2022Assignee: SK hynix Inc.Inventor: Sung Hyun Hwang
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Patent number: 11443818Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.Type: GrantFiled: May 31, 2019Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Alberto Troia
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Patent number: 11430528Abstract: A change in a read window of a group of memory cells of a memory device that has undergone a plurality of program/erase cycles (PECs) can be determined. read voltage can be determined based at least in part on the determined change in the read window.Type: GrantFiled: August 25, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo′ Righetti
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Patent number: 11393508Abstract: Devices and methods for accessing resistive change elements in a resistive change element array to determine resistive states of the resistive change elements are disclosed. According to some aspects of the present disclosure the devices and methods access resistive change elements in a resistive change element array through a variety of operations. According to some aspects of the present disclosure the devices and methods supply an amount of current tailored for a particular operation. According to some aspects of the present disclosure the devices and methods compensate for circuit conditions of a resistive change element array by adjusting an amount of current tailored for a particular operation to compensate for circuit conditions of the resistive change element array.Type: GrantFiled: May 10, 2019Date of Patent: July 19, 2022Assignee: Nantero, Inc.Inventor: Jia Luo
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Patent number: 11367487Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.Type: GrantFiled: November 25, 2019Date of Patent: June 21, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Won Park, Won Bo Shim, Bong Soon Lim
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Patent number: 11367485Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.Type: GrantFiled: September 29, 2020Date of Patent: June 21, 2022Assignee: Western Digital Technologies, Inc.Inventors: Idan Alrod, Eran Sharon, Alon Marcu, Yan Li
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Patent number: 11355193Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: October 6, 2020Date of Patent: June 7, 2022Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Patent number: 11355188Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.Type: GrantFiled: April 30, 2021Date of Patent: June 7, 2022Assignee: SanDisk Technologies LLCInventors: Michael K. Grobis, Daniel Bedau
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Patent number: 11342031Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.Type: GrantFiled: August 28, 2020Date of Patent: May 24, 2022Assignees: STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Marco Pasotti, Dario Livornesi, Roberto Bregoli, Vikas Rana, Abhishek Mittal
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Patent number: 11327112Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.Type: GrantFiled: January 12, 2021Date of Patent: May 10, 2022Assignee: SK hynix Inc.Inventor: Yun Seok Hong
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Patent number: 11302405Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.Type: GrantFiled: December 10, 2019Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Sriram Natarajan, Shankar Natarajan, Yihua Zhang, Hinesh K. Shah, Rohit S. Shenoy, Arun Sitaram Athreya
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Patent number: 11269551Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of planes. The peripheral circuit is configured to perform a plane interleaving operation for the plurality of planes. The control logic controls the peripheral circuit to reset an operation of at least one plane of the plurality of planes based on a type of an operation reset command received by the control logic.Type: GrantFiled: March 12, 2020Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventor: Ki Cheol Son
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Patent number: 11244714Abstract: A method of writing to a magnetic random access memory cell includes applying an alternating current signal to the magnetic random access memory cell having a first magnetic orientation, and applying a direct current pulse to the magnetic random access memory cell to change the magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.Type: GrantFiled: February 8, 2021Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Duen-Huei Hou
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Patent number: 11227640Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.Type: GrantFiled: May 8, 2020Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Semiconductor device with a diagnosing section that diagnoses correction memory and sensor apparatus
Patent number: 11211133Abstract: To detect deterioration of a correction memory, provided is a semiconductor device including the correction memory that stores therein correction data for correcting a correction target; a correcting section that corrects a detection value of a sensor element, using correction data read from the correction memory; a diagnosing section that diagnoses the correction memory, using the correction data read from the correction memory; and a control section that controls reading conditions used when reading the correction data from the correction memory, wherein the control section causes a first reading condition, used when reading the correction data for correcting a correction target, to differ from a second reading condition, which is used when reading the correction data for the diagnosis.Type: GrantFiled: May 24, 2020Date of Patent: December 28, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazuhiro Matsunami, Katsuhiro Shimazu -
Patent number: 11195590Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.Type: GrantFiled: March 24, 2020Date of Patent: December 7, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Patent number: 11195562Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.Type: GrantFiled: May 8, 2020Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Patent number: 11189352Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of a memory cell of the memory component. A program targeting operation is performed on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.Type: GrantFiled: March 7, 2019Date of Patent: November 30, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Bruce A. Liikanen, Larry J. Koudele, Michael Sheperek
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Patent number: 11175983Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.Type: GrantFiled: March 18, 2020Date of Patent: November 16, 2021Assignee: Western Digital Technologies, Inc.Inventors: Guangming Lu, Kent D. Anderson, Anantha Raman Krishnan, Shafa Dahandeh
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Patent number: 11170861Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.Type: GrantFiled: July 27, 2020Date of Patent: November 9, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chia-Fu Chang, Hung-Yi Liao
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Patent number: 11152038Abstract: Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.Type: GrantFiled: February 17, 2020Date of Patent: October 19, 2021Assignee: QUALCOMM INCORPORATEDInventors: Anil Chowdary Kota, Keejong Kim, Hochul Lee
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Patent number: 11145368Abstract: A memory device has a switch matrix with a power supply input, a control input and a power supply output, a random access memory with a power supply connection coupled with the power supply output of the switch matrix. The switch matrix has a capacitor being chargeable by a power supply and upon receiving a control signal through the control input, the switch matrix is designed to decouple the capacitor from the power supply and the random access memory and to couple the capacitor through the power supply output with the random access memory in reverse polarity thereby providing a negative power supply to the power supply output.Type: GrantFiled: July 2, 2020Date of Patent: October 12, 2021Assignee: Microchip Technology IncorporatedInventor: Ajay Kumar
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Patent number: 11127473Abstract: A memory apparatus and a data reading method thereof are provided. In the method, a plurality of memory cells of the memory apparatus are read to obtain read data, in which a threshold voltage of each memory cell is sensed and respectively compared with a first reference voltage and a second reference voltage to determine bit values. The first reference voltage and the second reference voltage are used to distinguish different states of the memory cell and the second reference voltage is larger than the first reference voltage. The bit values of the memory cells having the threshold voltage between the first reference voltage and the second reference voltage in the read data are gradually changed and syndromes of the changed read data are calculated. The read data is corrected according to values of the syndromes.Type: GrantFiled: April 14, 2020Date of Patent: September 21, 2021Assignee: Winbond Electronics Corp.Inventor: Wen-Chiao Ho
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Patent number: 11127471Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.Type: GrantFiled: July 23, 2019Date of Patent: September 21, 2021Assignee: SK hynix Inc.Inventors: Xuanxuan Lu, Fan Zhang, Chenrong Xiong, Haobo Wang, Meysam Asadi
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Patent number: 11107540Abstract: Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.Type: GrantFiled: February 14, 2020Date of Patent: August 31, 2021Assignee: Sandisk Technologies LLCInventors: Jayavel Pachamuthu, Dengtao Zhao