Reference Signal (e.g., Dummy Cell) Patents (Class 365/185.2)
  • Patent number: 11211133
    Abstract: To detect deterioration of a correction memory, provided is a semiconductor device including the correction memory that stores therein correction data for correcting a correction target; a correcting section that corrects a detection value of a sensor element, using correction data read from the correction memory; a diagnosing section that diagnoses the correction memory, using the correction data read from the correction memory; and a control section that controls reading conditions used when reading the correction data from the correction memory, wherein the control section causes a first reading condition, used when reading the correction data for correcting a correction target, to differ from a second reading condition, which is used when reading the correction data for the diagnosis.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: December 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kazuhiro Matsunami, Katsuhiro Shimazu
  • Patent number: 11195590
    Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 7, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yali Song, XiangNan Zhao, Ying Cui
  • Patent number: 11195562
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Patent number: 11189352
    Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of a memory cell of the memory component. A program targeting operation is performed on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 30, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Bruce A. Liikanen, Larry J. Koudele, Michael Sheperek
  • Patent number: 11175983
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guangming Lu, Kent D. Anderson, Anantha Raman Krishnan, Shafa Dahandeh
  • Patent number: 11170861
    Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 9, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Fu Chang, Hung-Yi Liao
  • Patent number: 11152038
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 19, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Anil Chowdary Kota, Keejong Kim, Hochul Lee
  • Patent number: 11145368
    Abstract: A memory device has a switch matrix with a power supply input, a control input and a power supply output, a random access memory with a power supply connection coupled with the power supply output of the switch matrix. The switch matrix has a capacitor being chargeable by a power supply and upon receiving a control signal through the control input, the switch matrix is designed to decouple the capacitor from the power supply and the random access memory and to couple the capacitor through the power supply output with the random access memory in reverse polarity thereby providing a negative power supply to the power supply output.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Microchip Technology Incorporated
    Inventor: Ajay Kumar
  • Patent number: 11127471
    Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Xuanxuan Lu, Fan Zhang, Chenrong Xiong, Haobo Wang, Meysam Asadi
  • Patent number: 11127473
    Abstract: A memory apparatus and a data reading method thereof are provided. In the method, a plurality of memory cells of the memory apparatus are read to obtain read data, in which a threshold voltage of each memory cell is sensed and respectively compared with a first reference voltage and a second reference voltage to determine bit values. The first reference voltage and the second reference voltage are used to distinguish different states of the memory cell and the second reference voltage is larger than the first reference voltage. The bit values of the memory cells having the threshold voltage between the first reference voltage and the second reference voltage in the read data are gradually changed and syndromes of the changed read data are calculated. The read data is corrected according to values of the syndromes.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 21, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Chiao Ho
  • Patent number: 11107540
    Abstract: Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 31, 2021
    Assignee: Sandisk Technologies LLC
    Inventors: Jayavel Pachamuthu, Dengtao Zhao
  • Patent number: 11106396
    Abstract: A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 31, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Kai Hsu, Teng-Hao Yeh, Ming-Liang Wei, Hang-Ting Lue
  • Patent number: 11099931
    Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa
  • Patent number: 11081204
    Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
  • Patent number: 11081178
    Abstract: Reliability of stored data is improved without increasing power consumption in a case where a threshold of a control element in a memory cell changes. In a memory including the memory cell, a reference cell, and an access control unit, the memory cell changes from a non-conduction state to a conduction state according to an applied voltage at a threshold voltage and changes to a high resistance state and a low resistance state according to the voltage applied in the conduction state. The reference cell changes from a non-conduction state to a conduction state at a reference threshold voltage according to an applied voltage. The access control unit estimates that the reference threshold voltage measured in the reference cell is the threshold voltage of the memory cell and applies a voltage to the memory cell when accessing the memory cell.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: August 3, 2021
    Assignee: Sony Corporation
    Inventor: Haruhiko Terada
  • Patent number: 11056163
    Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 6, 2021
    Assignee: Arm Limited
    Inventors: El Mehdi Boujamaa, Cyrille Nicolas Dray
  • Patent number: 11048654
    Abstract: Systems, apparatus and methods are provided to combine multiple channels in a multi-channel memory controller to save area and reduce power and cost. An apparatus may comprise a first memory controller configured to access a first channel using a first protocol, a second memory controller configured to access a second channel using a second protocol that is different from the first protocol and a physical interface coupled to the first memory controller and a second memory controller. The physical interface may comprise a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 29, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Shawn Chen, Wei Jiang, Lin Chen
  • Patent number: 11036631
    Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 11024395
    Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 1, 2021
    Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
  • Patent number: 11011234
    Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 18, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Yi-Ching Liu
  • Patent number: 11004508
    Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Michael K. Grobis, Daniel Bedau
  • Patent number: 11004519
    Abstract: A memory controller having improved read performance controls a memory device including a plurality of memory cells. The memory controller includes a read operation controller, a history bias storage, and a read voltage setting circuit. The read operation controller read data stored selected memory cells among the plurality of memory cells. The history bias storage stores a plurality of history mean biases, which are mean biases of a plurality of threshold voltage distributions that the plurality of memory cells have, and a plurality of reference cell count values respectively corresponding to the plurality of threshold voltage distributions.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Seon Ju Lee, Min Hwan Moon
  • Patent number: 10998058
    Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 4, 2021
    Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
  • Patent number: 10990466
    Abstract: A system includes a memory circuitry configured to receive a command, and in response to the command: generate a first read result based on reading a set of memory cells using a first read voltage; and generate a second read result based on reading the set of memory cells using a second read voltage, wherein: the first read voltage and the second read voltage are separately associated with a read level voltage initially assigned to read the set of memory cells, and the first read result and the second read result are for calibrating the read level voltage.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen, Violante Moschiano
  • Patent number: 10991438
    Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 27, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
  • Patent number: 10986614
    Abstract: Various communication systems may benefit from an improved signaling protocol. For example, communication systems may benefit from an improved network support for a narrowband internet of things in a hosting long term evolution carrier. A method, in certain embodiments, includes shifting a frequency of a downlink long term evolution channel by a pre-determined amount. The shift causes a duplex distance between the downlink long term evolution channel and an uplink long term evolution channel to change. The method includes blanking at least one overlapping radio resource in at least one of the uplink long term evolution channel or an uplink narrowband internet of things channel. The uplink narrowband internet of things channel and the uplink long term evolution channel at least partially overlap. In addition, the method includes receiving data on the uplink narrowband internet of things channel and an additional uplink narrowband internet of things channel at a network entity from a user equipment.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 20, 2021
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Gunter Wolff, Man Hung Ng, Iwajlo Angelow
  • Patent number: 10964387
    Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Artur Antonyan
  • Patent number: 10964399
    Abstract: A one-time programmable (OTP) memory device including: a cell array circuit including an OTP cell array and dummy cell block, the OTP cell array includes OTP memory cells coupled to bit-lines, read word-lines and voltage word-lines and the dummy cell block is coupled to the read word-lines and voltage word-lines; a row decoder coupled to the dummy cell block and the OTP cell array through the read word-lines and voltage word-lines; a column decoder coupled to the OTP cell array through the bit-lines; a write-sensing circuit coupled to the column decoder; and a control circuit to control the cell array circuit, row decoder and write-sensing circuit based on a command and address, the cell array circuit further includes an isolation circuit to cut off first and second voltages which are transferred to the OTP cell array from the row decoder, in response to control codes in a test mode.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Yeol Ha
  • Patent number: 10957412
    Abstract: A memory device includes a memory cell array including a plurality of strings, a peripheral circuit coupled to the memory cell array and configured for sequentially performing a program voltage apply operation, a program verify operation, and a hole injection operation on the plurality of strings, and a control logic configured for controlling an operation of the peripheral circuit, wherein the control logic controls the operation of peripheral circuit to generate Gate Induced Drain Leakage (GIDL) at a channel under a select transistor of each of the plurality of strings during the hole injection operation.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Byung In Lee, Sang Heon Lee
  • Patent number: 10950617
    Abstract: A memory device includes a plurality of word lines spaced from one another in a first direction, a first insulating film provided between adjacent word lines, a plurality of select gates located above the plurality of word lines in the first direction, a first intermediate electrode provided between the plurality of word lines and the select gates, a second insulating film provided between the first intermediate electrode and the select gates, a semiconductor pillar extending through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gates, and extending in the first direction, and a charge retention film located between each of the plurality of word lines and the semiconductor pillar, wherein the second insulating film has a second thickness in the first direction that is greater than a first thickness of the first insulating film in the first direction.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 10910030
    Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Artur Antonyan, Hyuntaek Jung, Suk-Soo Pyo
  • Patent number: 10903861
    Abstract: A method of generating soft decision detection parameters for a plurality of received signals. The method comprises defining a hard decision boundary and a plurality of quantisation intervals wherein each quantisation interval extends from the hard decision boundary by an interval distance, selecting a log likelihood value from a set of log likelihood values for each received signal based on the quantisation interval in which the received signal is detected, performing a soft decoding using a plurality of log likelihood values, adjusting the set of log likelihood values based on a result of the soft decoding, determining an error probability for a quantisation interval, comparing the error probability against a target error probability and adjusting the interval distance in order to obtain the target error probability.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: January 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Memory Corporation
    Inventors: Magnus Stig Torsten Sandell, Amr Ismail
  • Patent number: 10896703
    Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Vijayakrishna J. Vankayala
  • Patent number: 10878909
    Abstract: A semiconductor device includes: a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors; one or more dummy word lines coupled to the one or more dummy transistors; and a plurality of select lines respectively coupled to the plurality of select transistors. When a program voltage is applied to a selected dummy word line among the one or more dummy word lines, a first dummy word line voltage may be applied to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Un Sang Lee
  • Patent number: 10861564
    Abstract: A memory circuit and a data bit status detector thereof are provided. The data bit status detector includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sense amplifying circuit has a first sense input end and a second sense input end. The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides the first impedance between the first sense input end and a reference grounding end according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides the second impedance between the second sense input end and the reference grounding end according to the bias voltages.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 8, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Zhe-Yi Lin, Wen-Chiao Ho
  • Patent number: 10777286
    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
  • Patent number: 10770125
    Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Adam D. Johnson
  • Patent number: 10762964
    Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10734056
    Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: El Mehdi Boujamaa, Cyrille Nicolas Dray
  • Patent number: 10733047
    Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Mostafa El Gamal, Jim Fitzpatrick
  • Patent number: 10714185
    Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Umberto Di Vincenzo
  • Patent number: 10706897
    Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chandra C. Varanasi
  • Patent number: 10685702
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Patent number: 10672478
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 10650901
    Abstract: An electronic device includes a controller, a non-transitory computer-readable storage medium including memory cells having a plurality of threshold voltage distributions and storing operation codes executable by the controller.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Nam Yoo
  • Patent number: 10636496
    Abstract: A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Ching Li, Yi-Ching Liu
  • Patent number: 10629247
    Abstract: Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 21, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Salil Kale, Shreejith Kv, Aneesh Puthoor, Gopu S, Narayan K
  • Patent number: 10580500
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Jae Hyuk Bang
  • Patent number: 10580485
    Abstract: Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions. The method also includes determining a bias value based on the selected bias function and the wordline. The method also includes adjusting a read level in the non-volatile memory based on the bias value. The method also includes performing the memory access operation on the wordline of the non-volatile memory using the adjusted read level. The bias functions may be linear functions and adjusted in response to detecting a recalibration condition.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Alexander Bazarsky, Tomer Tzvi Eliash, David Rozman, Eran Sharon, Arthur Shulkin
  • Patent number: 10566068
    Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoji Kashihara