Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

Abstract: A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

Abstract: A signal generator includes a first amplifier for outputting an amplified voltage in response to a reference voltage and a feedback voltage, a divider circuit for dividing the amplified voltage to generate a divided voltage and the feedback voltage, and a buffer group for outputting a common sensing signal in response to the amplified voltage and outputting a sensing signal in response to the divided voltage, and a memory device including the signal generator.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a memory block including a plurality of pages, a voltage generator configured to generate a program voltage or a verify voltage applied to a selected page among the plurality of pages, a page buffer connected to the selected page through bit lines and configured to perform a precharge operation, an evaluation operation, and a sensing operation on the bit lines during a verify operation, and a control circuit configured to store page addresses of slow pages of which a program operation speed for each is slower than an average program speed of the plurality of pages, and adjust an evaluation time of the evaluation operation according to the page addresses.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.

Abstract: Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

Abstract: A device includes a memory array and a sense amplifier (SA) coupled with the memory array and with an input/output (I/O) data line. The SA is to receive bits of data over the I/O data line in association with a program operation. A digital-to-analog converter (DAC) is coupled with the SA, the DAC to convert the bits of data to an analog voltage value. An analog memory element is coupled with the DAC, the analog memory element to store the analog voltage value for a period of time until the bits of data are programmed to the memory array.

Abstract: A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor.

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Abstract: In various aspects, a voltage supply circuit may include a first controlled voltage converter circuit including a first voltage converter and a first control circuit, wherein the first control circuit is configured to receive an input voltage and control the first voltage converter to output a first output voltage having a predefined relationship to the received input voltage; and a second controlled voltage converter circuit including a second voltage converter and a second control circuit, wherein the second control circuit is configured to receive the first output voltage and control the second voltage converter to output a second output voltage having a predefined relationship to the received first output voltage.

Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.

Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Abstract: A non-volatile memory device includes a plurality of memory blocks and a dummy block configured to form a pool capacitor for suppressing power noise. The dummy block includes a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region. The alternating dummy layer stack includes multiple conductive layers and multiple dielectric layers alternately laminated on one another.

Abstract: A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

Abstract: A memory device includes a bit line precharge circuit configured to precharge bit lines of a memory array in response to a clock pulse. A controller is configured to output the clock pulse to the bit line precharge circuit, and to output a first word line enable signal to a word line driver. The first word line enable signal is delayed by a first delay time from the clock pulse, and a second word line enable signal is delayed by a second delay time from the clock pulse.

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

Abstract: An active load circuit that includes a diode bridge having first through fourth nodes, wherein a voltage buffer is connected with the first node, a source current mirror is connected with the second node, the third node is configured for connection to a device under test (DUT), and a sink current mirror is connected with the fourth node. A first current mirror is connected with the source current mirror, and a second current mirror is connected with the sink current mirror. A first differential pair is connected with the first current mirror and includes an input connected with the DUT and a second input connected with the input voltage. A second differential pair is connected with the second current mirror and includes a first input connected with the DUT and a second input connected with the input voltage.

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

Abstract: A semiconductor device according to an embodiment includes first and second drain select transistors, first and second source select transistors, first and second memory cell transistors, third and fourth memory cell transistors, first and second bit lines, first to third select gate line, first and second word lines, and a controller. The controller is configured to execute, in the program loop, a program operation, a recovery operation and a verify operation in sequence. In the write operation of the first memory cell transistor, the controller is configured, at a first time of the recovery operation, to: apply a first voltage to the first select gate line; apply a second voltage to the third select gate line; and apply a third voltage to the first bit line.

Abstract: A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.

Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.

Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.

Abstract: According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.

Abstract: A sense amplifier for a memory circuit is presented that can reduce sensing times by introduction of a local reference generator. The sense amplifier includes two capacitors that are pre-charged prior to a sensing operation. A first of the capacitors is connected so that it can discharge through a selected memory cell at a rate dependent on the conductivity of the selected memory cell. After a sensing interval in which the first capacitor can discharge through the selected memory cell, the voltage level on the first capacitor is compared with the voltage level on the second capacitor to determine the result of the sensing operation.

Abstract: A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Abstract: An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of first logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

Abstract: A memory device comprises a memory cell array with memory cells arranged in a cell string coupled to a metal bit line, a sense amplifier for providing a sensing current to the memory cell array, and a memory controller for controlling the sense amplifier to provide the sensing current to access data during a memory access cycle. The memory controller performs operations comprising: during a pre-charging stage of the memory access cycle, providing a pre-charging voltage to the sense amplifier to drive the sense amplifier such that a particular voltage is provided to the memory cell array; during a first sensing stage, providing the pre-charging voltage to the sense amplifier; and during a second sensing stage, providing a sensing voltage to drive the sense amplifier such that the particular voltage provided to the memory cell array is maintained.

Abstract: Methods, systems, and devices for memory management associated with charge leakage in a memory device are described. A memory device may identify a charge leakage associated with one or more memory cells or access lines, and may determine whether to invert a logic state stored by a memory cell or a set of memory cells to improve the likelihood that the memory cells are read properly in the presence of charge leakage. In some examples, the memory device may also store an indication that the complement of the detected logic state was written, such as a bit flip indication, which may correspond to one memory cell or a set of memory cells.

Abstract: A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices.

Abstract: A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.

Abstract: A method of programming a NAND flash memory device includes: a programming voltage generation circuit applying an initial programming voltage pulse to a predetermined page of NAND flash memory; a controller verifying a plurality of verification levels of the predetermined page, the plurality of verification levels being less than a first-state verification voltage of verifying a lowest program state of the predetermined page; the controller determining a magnitude of a subsequent programming voltage pulse upon one of the plurality of verification levels of the predetermined page passing a verification; and the programming voltage generation circuit applying the subsequent programming voltage pulse to the predetermined page.

Abstract: Methods of operating a memory, as well as memory configured to perform such method, include applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Abstract: A high voltage generator includes a voltage converting device configured to increase a level of an input voltage and output an output voltage having a level higher than the level of the input voltage. The high voltage generator also includes a precharge controller configured to gradually increase the level of the input voltage up to a level of an external voltage based on a reference voltage and the output voltage.