Verify Signal Patents (Class 365/185.22)
  • Patent number: 10957390
    Abstract: A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 23, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Naoaki Sudo
  • Patent number: 10957402
    Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10950311
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Patent number: 10937502
    Abstract: A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshifumi Hashimoto
  • Patent number: 10923198
    Abstract: Provided herein may be a memory device and a memory system including the same. The memory device may include a logic group configured to generate and output driver control signals based on data received from an external device; and an internal power supply circuit configured to control current corresponding to an internal power supply voltage in response to the driver control signals, wherein the internal power supply circuit increases the current corresponding to the internal power supply voltage as the number of first data in the received data increases.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Sok Kyu Lee
  • Patent number: 10902920
    Abstract: Method of operating an integrated circuit device might include applying a first voltage level to a first conductor while applying a second voltage level to a second conductor, applying a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and applying a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 10902924
    Abstract: A memory system includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to apply a read voltage to a selected word line coupled to a selected memory cell among the memory cells, and apply a pass voltage to unselected word lines coupled to unselected memory cells other than the selected memory cell among the memory cells, during a read operation; and a controller configured to control the peripheral circuit, and apply a variable voltage level of the pass voltage based on status information of a target memory block which is the target of the read operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Se Chang Park, Jong Wook Kim
  • Patent number: 10892020
    Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Hioka, Tsukasa Kobayashi, Koji Kato, Yuki Shimizu, Hiroshi Maejima
  • Patent number: 10891080
    Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 12, 2021
    Assignee: MENTIUM TECHNOLOGIES INC.
    Inventors: Farnood Merrikh Bayat, Mirko Prezioso
  • Patent number: 10878895
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 10838665
    Abstract: A control device for a non-volatile memory express (NVMe) over fabric architecture is provided. The control device comprises a network adapter and a processor coupled to the network adapter by a bus. Data is transmitted between the control device and a storage device in the NVMe over fabric architecture. The processor is configured to obtain an available storage space of the storage device, determine whether a storage space required by a first data to be transmitted according to a first data read/write command is equal to or less than the available storage space, and send the first data read/write command to the storage device if the storage space required by the first data is equal or less than to the available storage space and suspend sending of the first data read/write command if the storage space occupied by the first data is greater than the available storage space.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: November 17, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Victor Gissin, Xin Qiu, Pei Wu, Huichun Qu, Jinbin Zhang
  • Patent number: 10839911
    Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo Ogura, Hideto Horii
  • Patent number: 10839924
    Abstract: There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hun Lee
  • Patent number: 10832765
    Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 10825529
    Abstract: A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 3, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wen-Ming Hsu, Nai-Ping Kuo, Chun-Hsiung Hung
  • Patent number: 10825369
    Abstract: An electro-optical device includes a pre-charge circuit configured to supply a pre-charge signal to a first and second signal line at different timings based on a pre-charge control signal, and an inspection circuit configured to output, to the pre-charge circuit, an inspection control signal indicating whether a target is to be inspected in an inspection operation. The pre-charge circuit includes a first switch, an electrical coupling state between the first signal line and a pre-charge power supply line based on a first coupling control signal, a second switch, an electrical coupling state between the second signal line and the pre-charge power supply line based on a second coupling control signal, a first signal to output the first coupling control signal to the first switch, and a second signal to output the second coupling control signal to the second switch based on the inspection control signal and the pre-charge control signal.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 3, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 10825372
    Abstract: A display device includes a panel. The panel includes a display array and a first scan line group. The display array displays a first image and a second image following the first image, and has a first regulation array. The first scan line group is arranged corresponding to the first regulation array. There is a blanking period existed between a first update period corresponding to the first image and a second update period corresponding to the second image. The blanking period has a first sub-period. The first scan line group sends a first scan signal to the first regulation array in the first sub-period.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 3, 2020
    Assignee: INNOLUX CORPORATION
    Inventor: Chien-Hsueh Chiang
  • Patent number: 10818358
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 10818362
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Patent number: 10811101
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 10811111
    Abstract: Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: October 20, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Chao Zhang
  • Patent number: 10796779
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Maejima, Noboru Shibata
  • Patent number: 10796753
    Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 6, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Shaw-Hung Ku, Yin-Jen Chen
  • Patent number: 10796767
    Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changyeon Yu, Minsu Kim, Hyun-Wook Park, Bongsoon Lim
  • Patent number: 10796777
    Abstract: Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 6, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Chao Zhang, Yanxia Lin
  • Patent number: 10748639
    Abstract: A controller includes a processor suitable for performing a first erase operation on a target memory block; a tester suitable for performing a test operation to apply test voltages to selected points of word lines included in the target memory block; a counter suitable for counting the numbers of error memory cells sensed through the test voltages at the selected points; and a skipper suitable for setting test skip information based on the numbers of error memory cells.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Yang-Hyeon Kwon
  • Patent number: 10740226
    Abstract: A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Jung-Hyun Kwon, Sung-Eun Lee
  • Patent number: 10734085
    Abstract: There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hun Lee
  • Patent number: 10734086
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Sang Hune Jung
  • Patent number: 10726932
    Abstract: A storage device includes a memory device configured to store program pulse information indicating whether the number of program pulses applied to selected memory cells during a program operation exceeds a reference value; and a memory controller configured to determine whether the probability of a growing defect occurring in the selected memory cells is present based on the program pulse information.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Un Sang Lee
  • Patent number: 10720222
    Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10706944
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jeong So, Dong-Hwan Lee, Seong-Hyeog Choi, Eun-Chu Oh, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon
  • Patent number: 10699790
    Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Krishna K. Parat, Pranav Kalavade, Koichi Kawai, Akira Goda
  • Patent number: 10692559
    Abstract: A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael T. Brady
  • Patent number: 10672459
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Arm Limited
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10665301
    Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 26, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Ashish Baraskar, Vinh Diep
  • Patent number: 10658059
    Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Griffin, Dustin J. VanStee
  • Patent number: 10643710
    Abstract: Apparatuses, systems, methods, and computer program products for enhanced erase retry of a non-volatile storage device are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a verification component configured to detect that an erase operation performed on an erase block of a non-volatile storage device is unsuccessful. A controller includes a parameter component configured to adjust one or more erase parameters for an erase operation. One or more erase parameters may be associated with one or more select gate drain storage cells of an erase block. A controller includes an erase component configured to retry an erase operation on an erase block with one or more adjusted erase parameters.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Divya Prasad, Sainath Viswasarai, Gopu S, Swaroop Kaza, Piyush Anil Dhotre, Chittoor Devarajan Sunilkumar
  • Patent number: 10636503
    Abstract: An apparatus includes a programming circuit configured to deliver a series of program loops to a memory cell. The apparatus further includes a sensing circuit configured to sense an electrical characteristic of the memory cell for a sensing time during each program loop. The apparatus also includes an alteration circuit configured to alter the sensing time of a subsequent program loop in response to a programming condition.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10629276
    Abstract: There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hun Lee
  • Patent number: 10614899
    Abstract: A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Antonino Pollio, Fulvio Rori
  • Patent number: 10601546
    Abstract: A dynamic interleaver performs a read operation to identify bit lines with high failures, and form groups of data bits for parity bits computation, such that each group includes at most one data bit from the bit lines with high failures. Thus, the interleave selects the bit lines with high failures based on a most recent read test, and can be adjusted according to the conditions of the storage device.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 24, 2020
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Chenrong Xiong, Fan Zhang, Xuanxuan Lu
  • Patent number: 10599516
    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10593407
    Abstract: A byte-programming method for programming data from a page register to a non-volatile memory array includes reading data of a selected byte in the page register and programming the data to the memory cells of the non-volatile memory corresponding to a selected column address; determining whether to update an array column address according to the selected column address, which includes: determining whether the data of the selected byte matches specified content; when the data of the selected byte matches the specified content, not updating the array column address; and when the data of the selected byte does not match the specified content, updating the array column address according to the selected column address; and determining whether the selected column address is the last column address.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Hung-Hsueh Lin
  • Patent number: 10586587
    Abstract: According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that controls the first circuit, wherein in a sequence in which the second circuit writes first data in the memory cell, the first circuit generates a first current of a first current value, and determines data stored in the memory cell based on the first current and a second current flowing in the memory cell, and in a sequence in which the second circuit writes second data different from the first data in the memory cell, the first circuit generates a third current of a second current value different from the first current value, and determines data stored in the memory cell based on the third current and the second current.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 10, 2020
    Assignees: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiaki Dozaka
  • Patent number: 10586601
    Abstract: A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. The controller is configured to determine a read voltage for a target memory cell by selecting a tracking parameter based on a word line connected to the target memory cell and an elapsed time from a previous access to a group of memory cells including the target memory cell, and executing a tracking process on the memory cells also connected to the word line connected to the target memory cell using the selected tracking parameter.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazutaka Takizawa, Masaaki Niijima
  • Patent number: 10580486
    Abstract: A method of operating a memory device to read data may include determining, in a first read interval associated with a first read operation, a threshold voltage distribution of a most significant program state of a target logical memory page included in a first physical memory page among a plurality of physical memory pages, the first read operation being an operation of reading the target logical memory page of the first physical memory page; transmitting, to a memory controller, a distribution determination result, the distribution determination result being related to the threshold voltage distribution; receiving, from the memory controller, offset levels corrected based on the distribution determination result; and adjusting a read voltage based on offset levels prior to performing a second read operation on a second physical memory page among the plurality of physical memory pages.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-su Kim, Dae-seok Byeon
  • Patent number: 10566062
    Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Shang-Chi Yang
  • Patent number: 10558371
    Abstract: An apparatus, system, and method are disclosed for data block usage information synchronization for a non-volatile storage volume. The method includes referencing first data block usage information for data blocks of a non-volatile storage volume managed by a storage manager. The first data block usage information is maintained by the storage manager. The method also includes synchronizing second data block usage information managed by a storage controller with the first data block usage information maintained by the storage manager. The storage manager maintains the first data block usage information separate from second data block usage information managed by the storage controller.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: February 11, 2020
    Assignee: FIO Semiconductor Technologies, LLC
    Inventors: David Flynn, David Atkisson, Drex Dixon, Jonathan Flynn, Brandon Hansen
  • Patent number: 10553291
    Abstract: Provided is a nonvolatile memory device and an operating method thereof. The operating method for programming a first memory block from among a plurality of memory blocks includes: programming a first word line connected to the first memory block by sequentially executing first to Nth (N is a natural number) programming loops; applying a voltage generated by regulating a first pump voltage of a first charge pump to the first word line as a dummy verifying voltage after the programming is completed; generating a first detection count based on the first pump voltage and a first reference voltage; and outputting a bad block setting signal for setting the first memory block as a bad block based on a result of comparing the first detection count with the first reference count.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yun Lee, Il-han Park, Jun-yong Park, Byung-soo Kim