Verify Signal Patents (Class 365/185.22)
  • Patent number: 11545193
    Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Yeong Jo Mun
  • Patent number: 11532369
    Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Hee Joo Lee
  • Patent number: 11508443
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, and a peripheral circuit that performs a program operation of repeatedly performing a program loop. The program loop includes performing a program by applying a program voltage to memory cells selected from the plurality of memory cells, and a first verify by applying a plurality of verify voltages to the selected memory cells. The peripheral circuit completes the program operation in response to a success of the first verify, performs a second verify by applying an additional verify voltage different from the plurality of verify voltages to the selected memory cells, and determines the program operation has failed in response to a failure of the second verify.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-Ha Park, Hyungsuk Kim
  • Patent number: 11507816
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11475972
    Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younghwi Yang, Ilhan Park, Jinyoung Kim, Sehwan Park, Dongmin Shin
  • Patent number: 11462280
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including receiving a read command to perform a read operation on a block of the memory device, determining a pass-through voltage for the block based on a metadata table, and performing the read operation by applying a read reference voltage to a selected wordline of the block and applying the pass-through voltage to a plurality of unselected wordlines of the block.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 4, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy
  • Patent number: 11430522
    Abstract: Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Silvia Beltrami, Angelo Visconti
  • Patent number: 11423986
    Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11423960
    Abstract: A memory device is disclosed, including a first switch and multiple first memory cells that are arranged in a first column, a second switch and multiple second memory cells that are arranged in a second column, a first data line and a second data line. The first data line is coupled to the first memory cells and the second memory cells. The second data line is coupled connected to the first memory cells and the second memory cells. The first switch transmits a data signal in the first data line in response to a control signal. The second switch outputs the data signal received from the second data line in response to the control signal.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11417406
    Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Jason Lee Nevill, Tommaso Vali
  • Patent number: 11417393
    Abstract: A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 16, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Sujjatul Islam, Muhammad Masuduzzaman, Ravi Kumar
  • Patent number: 11410723
    Abstract: Provided herein may be a method of operating a semiconductor device including memory cells each storing multi-bit data. The method includes receiving data that is to be programmed in a memory cell selected from the memory cells; and applying a program pulse to the selected memory cell, the program pulse being determined depending on a logic state of the data and being selected from a group including a first program pulse having a positive polarity, a second program pulse having the positive polarity and having at least one of a peak level, a peak period, and a falling slew rate different from those of the first program pulse, a third program pulse having a negative polarity, and a fourth program pulse having the negative polarity and having at least one of a peak level, a peak period, and a rising slew rate different from those of the third program pulse.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Hyun Han
  • Patent number: 11409941
    Abstract: A method of designing a semiconductor chip includes: acquiring first data including information about arrangement of a plurality of cells on the semiconductor chip; acquiring second data including information about routing between the plurality of cells and power and signal lines; and outputting a verification result by detecting an error of arrangement of the plurality of cells based on matching of the first data and the second data.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sunghoon Lee
  • Patent number: 11410729
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 11404132
    Abstract: A method for measuring interference in a memory device is provided. The method includes: programming a selected memory cell among a plurality of memory cells connected in series between a bit line and a source line; measuring a first noise value of the programmed selected memory cell; programming an adjacent memory cell adjacent to the selected memory cell among the plurality of memory cells; measuring a second noise value of the selected memory cell, after the programming of the adjacent memory cell is completed; and determining interference on the selected memory cell based on the first noise value and the second noise value. The first noise value and the second noise value are measured by detecting a low frequency noise of a cell current of the selected memory cell.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 2, 2022
    Assignees: SK hynix Inc., Korea University Research and Business Foundation, Seiong Campus
    Inventors: Jae Woo Lee, Soo Hyun Kim, Dong Hyun Kim, Dong Geun Park, Geun Soo Yang, Jung Chun Kim, Sae Yan Choi
  • Patent number: 11403042
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Patent number: 11398280
    Abstract: A method for a pre-lockout read for a reverse order read operation with lockout mode is disclosed. The method comprises: performing a pre-lockout read at a first sensing level to determine which memory cells of the set of memory cells are on in response to the first sensing level being applied to a selected word line; performing a first sensing operation on the selected word line at a second sensing level including sensing memory cells of the set of memory cells determined to be off in response to the pre-lockout read; and performing a second sensing operation on the selected word line at a third sensing level including sensing memory cells of the set of memory cells determined to be on in response to the pre-lockout read, where the first sensing level is of a value between the second sensing level and the third sensing level.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: July 26, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Huai-yuan Tseng, Ravi Kumar
  • Patent number: 11398277
    Abstract: A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: July 26, 2022
    Assignee: Kioxia Corporation
    Inventors: Takuya Kusaka, Daisuke Arizono, Yoshikazu Harada
  • Patent number: 11398289
    Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 26, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Tanmoy Roy, Anuj Grover
  • Patent number: 11398286
    Abstract: A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a block of memory cells The peripheral circuitry can perform first program-verify loops in response to a first write operation to a first word line in a word line group to program memory cells associated with the first word line to multiple states. The word line group includes one or more word lines. Then, the peripheral circuitry determines verification start loops of the multiple states based on sensing results in the first program-verify loops, and performs second program-verify loops with the determined verification start loops of the multiple states in response to a second write operation to a second word line in the word line group.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 26, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ke Jiang, Huamin Cao, Zilong Chen, Bin Xiang
  • Patent number: 11393535
    Abstract: Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 19, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani, Thuan Vu, Nhan Do, Vipin Tiwari
  • Patent number: 11367484
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yen Chun Lee, Nevil N. Gajera, Karthik Sarpatwari
  • Patent number: 11361834
    Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 14, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Ravi Kumar, Deepanshu Dutta
  • Patent number: 11355184
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 7, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Vipin Tiwari
  • Patent number: 11355209
    Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
  • Patent number: 11341048
    Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xinghui Duan, Guanzhong Wang, Xu Zhang, Eric Kwok Fung Yuen
  • Patent number: 11335423
    Abstract: A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a pre-defined number of blocks of the non-volatile memory, performing a read operation on a first block included in a first super block based on a first read level, storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful, receiving a read request for a second block of the first super block and an address of the second block from a host, and performing a read operation on the second block based on the history read level stored in the history buffer. The pre-defined number is at least two.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangsoo Cha, Suyong Jang
  • Patent number: 11333910
    Abstract: An electro-optical device includes a scanning line, a first signal line and a second signal line, a first pixel, a second pixel, a signal line driving circuit configured to supply an image signal to the first pixel and the second pixel, a first pre-charge control signal line configured to supply a first pre-charge control signal, a second pre-charge control signal line configured to supply a second pre-charge control signal, and a pre-charge circuit disposed between the first pre-charge control signal line and the second pre-charge control signal line and configured to supply a pre-charge signal to the first signal line and the second signal line, in which the pre-charge circuit includes a first switching unit configured to supply the pre-charge signal to the first signal line and a second switching unit configured to supply the pre-charge signal to the second signal line.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 17, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 11333945
    Abstract: This application discloses a display panel and a display apparatus. The display panel includes a substrate on which data lines, gate lines, pixels, and a gate driver chip are arranged, where the gate driver chip outputs gate enable signals to the gate lines to turn on the pixels; each row of pixels include a plurality of pixel groups, each of the pixel groups includes a first column of pixel and a second column of pixel, the first column of pixel and the second column of pixel are connected to the same data line, and the first column of pixel and the second column of pixel are connected to two different gate lines; and the channel width-to-length ratio of an active switch corresponding to the second column of pixel is greater than that corresponding to the first column of pixel.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 17, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Chuan Wu
  • Patent number: 11322222
    Abstract: A memory device includes at least one first register, a memory circuit, an analyzing circuit, and a control circuit. The memory circuit includes a plurality of bit cells. The analyzing circuit is configured to perform an analyzing process on the bit cells to generate an analyzing result. If the analyzing result indicates that a first bit cell of the bit cells fails, the control circuit establishes a repair process by controlling data to be written into the at least one first register and controlling the data to be read out from the at least one first register.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 3, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hsin-Cheng Ko
  • Patent number: 11315650
    Abstract: A memory system is provided to include a memory device and a memory controller configured to control the memory device. The memory device includes a first data latch storing information about a state of the memory cell and is configured to: execute a first verification operation and a second verification operation on the memory cell in response to receiving, from the memory controller, a suspend command to suspend a program operation being performed on the memory cell; store, in the first data latch, a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation; and execute, a resumption command to resume the program operation, a third verification operation, and restore the result value of the first verification operation and the result value of the second verification operation.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: April 26, 2022
    Inventors: Ju Yong Kim, Young Gyun Kim, Ki Woong Lee
  • Patent number: 11314452
    Abstract: A method of controlling an operation of a nonvolatile memory device includes monitoring multiple data streams having different stream identifiers to determine a stream data characteristic of each of the multiple data streams, determining a plurality of operation conditions based on a plurality of operation environments, respectively, and determining one of the plurality of operation conditions as a stream operation condition of each of the multiple data streams based on the stream data characteristics of each of the multiple data streams.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwoo Lim, Kyungduk Lee
  • Patent number: 11315648
    Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 26, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Dengtao Zhao, Huai-Yuan Tseng
  • Patent number: 11315644
    Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Pranav Kalavade, Rohit S. Shenoy, Golnaz Karbasian
  • Patent number: 11309394
    Abstract: A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinya Haraguchi
  • Patent number: 11309041
    Abstract: Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Ming Wang
  • Patent number: 11307799
    Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 19, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 11302375
    Abstract: A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes sending an initial translation map to a host system coupled to a memory component, receiving, from the host system, a modified translation map, and performing, by a processing device, a refresh operation of the memory component using the modified translation map.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 12, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Michael T. Brady
  • Patent number: 11302408
    Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a current sensing circuit configured to perform an individual current sensing operation according to a verify result of each of selected program states in an individual current sensing mode and perform an entire current sensing operation according to a verify result of the entire memory cells regardless of the selected program states after the individual current sensing operation is performed in a mixed current sensing mode, and a voltage generator configured to apply a program voltage to a selected word line connected to the memory cells during a first amount of time in the individual current sensing mode and apply the program voltage to the selected word line during a second amount of time greater than the first amount of time in the mixed current sensing mode, in response to the operation code.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11294596
    Abstract: A memory controller capable of controlling a memory device to perform a fine program operation, based on a time elapsing from a foggy program completion time and a position of a page on which a fine program is performed controls the memory device including a plurality of pages. The memory controller includes: a fine program timer for recording a foggy program completion time at which a foggy program completion response corresponding to a foggy program operation is received from the memory device, and outputting dummy program instruction information, based on an elapsing amount of time from the foggy program completion time; and a command controller for outputting a fine program command, based on the dummy program instruction information.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Gu Ji
  • Patent number: 11287992
    Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonghoon Woo, Soon Suk Hwang
  • Patent number: 11289168
    Abstract: According to an embodiment, a memory system including: a semiconductor memory configured to store data, a memory controller configured to issue a first command to suspend a first operation to the semiconductor memory which is executing the first operation, wherein the memory controller is configured to prohibit the issuance of the first command until a time in which the first operation is executed passes a first threshold, acquire a status of the semiconductor memory which is executing the first operation, and update the first threshold to a second threshold in accordance with the status.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Takashi Kondo
  • Patent number: 11289169
    Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 29, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao
  • Patent number: 11269703
    Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 8, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kentaro Shimada, Makio Mizuno
  • Patent number: 11250926
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 15, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Jianzhi Wu, Xiang Yang
  • Patent number: 11244735
    Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 8, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 11227660
    Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changyeon Yu, Minsu Kim, Hyun-Wook Park, Bongsoon Lim
  • Patent number: 11227659
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Patent number: 11227663
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: January 18, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Patent number: 11227657
    Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee