Drive Circuitry (e.g., Word Line Driver) Patents (Class 365/185.23)
  • Patent number: 11437110
    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Deepanshu Dutta, Huai-Yuan Tseng
  • Patent number: 11437088
    Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjae Kim, Jincheol Kim, Ahreum Kim, Homoon Shin, Dooho Cho, Yongsung Cho
  • Patent number: 11417376
    Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Kyung Park, Ji Hyun Seo, Hye Eun Heo
  • Patent number: 11417397
    Abstract: A control method of a non-volatile memory device is provided. The non-volatile memory device includes a memory array including a plurality of memory strings. Each memory string includes a plurality of memory cells connected in series. The control method includes applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period; and applying a program voltage signal to a selected word line connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jianquan Jia, Kun Fan
  • Patent number: 11398278
    Abstract: The present disclosure relates to a NOR flash memory circuit, a data writing method, a data reading method, and a data erasing method. The NOR flash memory circuit includes: a NOR memory array, a source voltage selection unit, a well voltage selection unit, a word line gating unit, a bit line gating unit, a data reading unit, and an analog voltage generating unit. During data writing, a source is floated, and a well electrode is connected to ground; and a first forward voltage is applied to a bit line where a memory cell to be written data into is located, and a second forward voltage is applied to a word line where the memory cell to be written data into is located. During data reading, a source is grounded, and well electrodes are grounded; and a third forward voltage is applied to a word line.
    Type: Grant
    Filed: September 11, 2021
    Date of Patent: July 26, 2022
    Assignee: CHINA FLASH CO., LTD.
    Inventors: Hong Nie, Yue Zhao
  • Patent number: 11398261
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 26, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
  • Patent number: 11374080
    Abstract: The present invention discloses a flexible display screen and a display device. The flexible display screen includes: a flexible display panel, a first flexible electromagnetic shielding layer and a bottom film disposed in that order on a side, opposite to a light-emitting side, of the flexible display panel; the organic electroluminescent flexible display panel has a bending area, and the bending area is provided with signal lines; the flexible display screen further includes: a second flexible electromagnetic shielding layer disposed on a light-emitting side of the flexible display panel and covering the signal lines, and a colloidal insulating layer covering the second flexible electromagnetic shielding layer; and the materials of the first flexible electromagnetic shielding layer and the second flexible electromagnetic shielding layer are both conductive materials with fluidity.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: June 28, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jiaxiang Zhang, Kang Wang, Xiaoxia Liu, Junhui Yang, Fuzheng Xie, Haotian Yang, Bin Zhang
  • Patent number: 11348642
    Abstract: A memory system has a non-volatile memory having a plurality of memory cells, and a controller configured to control writing, reading, and erasing of data into and from the non-volatile memory. The non-volatile memory includes a page for which the data is written and read to and from at least a part of the plurality of memory cells, and a block having a plurality of the pages. The controller manages a first block group including a plurality of the blocks and a second block group including a plurality of the first block groups, and generates a first parity for correcting an error occurring in the second block group by data in each of the plurality of first block groups in the second block group, and a second parity for correcting an error occurring in the first block group by data in the first block group.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventor: Mitsunori Tadokoro
  • Patent number: 11342024
    Abstract: A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
  • Patent number: 11336283
    Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: May 17, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Patent number: 11335415
    Abstract: Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 11322544
    Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwan Lee, Yongseok Kim, Taehun Kim, Seokhan Park, Satoru Yamada, Jaeho Hong
  • Patent number: 11264090
    Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 1, 2022
    Assignee: Kioxia Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 11264087
    Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 1, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Makoto Yabuuchi
  • Patent number: 11169587
    Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11158367
    Abstract: Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth W. Marr, Michael A. Smith
  • Patent number: 11146295
    Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yu-Hsiang Lin
  • Patent number: 11139030
    Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A plurality of blocks are connected together and selected for operations using a block select signal. A control circuit is configured to, after a read operation of memory cells of the block, hold a block select signal applied to a block select line to select a group of blocks having a same block select line at an on level. The control circuit can further discharge an unselected control gate in the group of blocks from a charged level to a lower level, lower than charged, prior to turning off the block select signal and charge the unselected control gate to a level greater than the lower level after the block select signal transitions from the on level to an off level.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Abhijith Prakash, Anubhav Khandelwal
  • Patent number: 11114938
    Abstract: A power supply circuit included in a computer system is configured to generate a particular voltage level on a regulated power supply node using multiple charge pump circuits coupled together via a regulation device to provide regulation. A first charge pump circuit is configured to, using a voltage of an input power supply node, generate an intermediate voltage level, which is regulated by the regulation device. The second charge pump is configured to generate a voltage level on the regulated power supply node using a regulated version of intermediate voltage level. An impedance of the regulation device is adjusted using results of comparing the voltage level of the regulated power supply node to a reference voltage.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Apple Inc.
    Inventors: Soheil Golara, Ali Mesgarani, Mansour Keramat, Seyedeh Sedigheh Hashemi
  • Patent number: 11081486
    Abstract: An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 3, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventor: Pierre C. Fazan
  • Patent number: 11061610
    Abstract: A memory system includes a controller and a semiconductor storage device a semiconductor storage device including a nonvolatile memory having a plurality of blocks and configured to execute commands from the controller. In response to a write command from the controller to write data into a block of the nonvolatile memory, the semiconductor storage device performs a write operation to write the data into the block of the nonvolatile memory, and upon detecting failure of writing the data into the block, the semiconductor storage device performs another write operation to write the data without notifying the controller of the failure of writing the data into the block.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Mitomi
  • Patent number: 11030130
    Abstract: A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 8, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chih-Wei Liang
  • Patent number: 11024642
    Abstract: A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Jun Hee Lim, Kohji Kanamori
  • Patent number: 11017862
    Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 25, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chih-Hsin Chen
  • Patent number: 11018579
    Abstract: A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 25, 2021
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Seungchul Jung, Sang Joon Kim, Junyoung Park, Yoonmyung Lee, Hyungmin Gi
  • Patent number: 10971235
    Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Hwan Park, Wan-Dong Kim
  • Patent number: 10964401
    Abstract: An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10887536
    Abstract: An image sensor includes a photoelectric conversion unit configured to receive light to generate an electric charge and provide the electric charge to a first node, a transfer transistor configured to provide a voltage level of the first node to a floating diffusion node in response to a first signal, a booster configured to increase a voltage level of the floating diffusion node in response to a second signal, a source follower transistor configured to provide the voltage level of the floating diffusion node to a second node, and a selection transistor configured to provide a voltage level of the second node to a pixel output terminal in response to a third signal. After the selection transistor is turned on, the booster is enabled, and before the transfer transistor is turned on, the booster is disabled.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Wook Lim, Eun Sub Shim, Kyung Ho Lee
  • Patent number: 10867684
    Abstract: Methods of operating a memory, and apparatus having a configuration to perform similar methods, might include connecting an access line of a plurality of access lines to an output of a voltage generation system and isolating the access line from an output of a voltage regulator, determining whether a particular voltage level of the voltage generation system makes a particular transition from a voltage level lower than a threshold to a voltage level higher than the threshold after connecting the access line to the output of the voltage generation system, and connecting the access line to the output of the voltage regulator in response to determining that the particular voltage level of the voltage generation system made the particular transition.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10867918
    Abstract: A power network includes a plurality of power switch units disposed in a first semiconductor layer, arranged in a plurality of columns along a first direction and a plurality of rows along a second direction. The power switch units in even rows are aligned with a center point of a horizontal space between adjacent two of the power switch units in the same row of the odd rows of the power switch units in the first direction. The power switch units in even columns are aligned with a center point of a vertical space between adjacent two of the power switch units in the same column of the odd columns of the power switch units in the second direction. The power network further includes a plurality of second connecting lines disposed in a fourth semiconductor layer and extending in the second direction.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 15, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jerming Lin, Lei Sun, Bing Li
  • Patent number: 10832784
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 10, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
  • Patent number: 10762969
    Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Matsunaga
  • Patent number: 10748591
    Abstract: A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 18, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chi-Yi Shao
  • Patent number: 10734070
    Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
  • Patent number: 10720212
    Abstract: A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10679708
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 9, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
  • Patent number: 10642579
    Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 5, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang
  • Patent number: 10585619
    Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
  • Patent number: 10528099
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10504563
    Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Byung S. Moon
  • Patent number: 10475811
    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10438653
    Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10431310
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10424383
    Abstract: A decoding method and a storage controller for a rewritable non-volatile memory module are provided. The method includes: choosing a target word line among a plurality of word lines, wherein preset data is programmed into a plurality of target memory cells of the target word-line; identifying a plurality of preset bit values according to the preset data; respectively using different X read voltage sets to read the target memory cells to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtain X deviation amount summation sets by comparing the X read bit value sets and the preset bit values; and determining N?1 optimized read voltages of an optimized read voltage set according to the X deviation amount summation sets.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 24, 2019
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10319443
    Abstract: A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10290335
    Abstract: The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. The semiconductor device may include a current path control unit configured to increase the speed at which the voltage of the main word line signal decreases.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Yub Lee, Sung Soo Chi
  • Patent number: 10255956
    Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Iwase, Ken Matsubara
  • Patent number: 10236041
    Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Thomas Kern, Christian Peters
  • Patent number: RE48013
    Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Bum Kim, Hyung Gon Kim, Chul Ho Lee, Hong Seok Chang
  • Patent number: RE49113
    Abstract: A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventors: Naoya Tokiwa, Hideo Mukai