Drive Circuitry (e.g., Word Line Driver) Patents (Class 365/185.23)
  • Patent number: 10887536
    Abstract: An image sensor includes a photoelectric conversion unit configured to receive light to generate an electric charge and provide the electric charge to a first node, a transfer transistor configured to provide a voltage level of the first node to a floating diffusion node in response to a first signal, a booster configured to increase a voltage level of the floating diffusion node in response to a second signal, a source follower transistor configured to provide the voltage level of the floating diffusion node to a second node, and a selection transistor configured to provide a voltage level of the second node to a pixel output terminal in response to a third signal. After the selection transistor is turned on, the booster is enabled, and before the transfer transistor is turned on, the booster is disabled.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Wook Lim, Eun Sub Shim, Kyung Ho Lee
  • Patent number: 10867918
    Abstract: A power network includes a plurality of power switch units disposed in a first semiconductor layer, arranged in a plurality of columns along a first direction and a plurality of rows along a second direction. The power switch units in even rows are aligned with a center point of a horizontal space between adjacent two of the power switch units in the same row of the odd rows of the power switch units in the first direction. The power switch units in even columns are aligned with a center point of a vertical space between adjacent two of the power switch units in the same column of the odd columns of the power switch units in the second direction. The power network further includes a plurality of second connecting lines disposed in a fourth semiconductor layer and extending in the second direction.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 15, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jerming Lin, Lei Sun, Bing Li
  • Patent number: 10867684
    Abstract: Methods of operating a memory, and apparatus having a configuration to perform similar methods, might include connecting an access line of a plurality of access lines to an output of a voltage generation system and isolating the access line from an output of a voltage regulator, determining whether a particular voltage level of the voltage generation system makes a particular transition from a voltage level lower than a threshold to a voltage level higher than the threshold after connecting the access line to the output of the voltage generation system, and connecting the access line to the output of the voltage regulator in response to determining that the particular voltage level of the voltage generation system made the particular transition.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10832784
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 10, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
  • Patent number: 10762969
    Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Matsunaga
  • Patent number: 10748591
    Abstract: A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 18, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chi-Yi Shao
  • Patent number: 10734070
    Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
  • Patent number: 10720212
    Abstract: A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10679708
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 9, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
  • Patent number: 10642579
    Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 5, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang
  • Patent number: 10585619
    Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
  • Patent number: 10528099
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10504563
    Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Byung S. Moon
  • Patent number: 10475811
    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10438653
    Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10431310
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10424383
    Abstract: A decoding method and a storage controller for a rewritable non-volatile memory module are provided. The method includes: choosing a target word line among a plurality of word lines, wherein preset data is programmed into a plurality of target memory cells of the target word-line; identifying a plurality of preset bit values according to the preset data; respectively using different X read voltage sets to read the target memory cells to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtain X deviation amount summation sets by comparing the X read bit value sets and the preset bit values; and determining N?1 optimized read voltages of an optimized read voltage set according to the X deviation amount summation sets.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 24, 2019
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10319443
    Abstract: A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10290335
    Abstract: The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. The semiconductor device may include a current path control unit configured to increase the speed at which the voltage of the main word line signal decreases.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Yub Lee, Sung Soo Chi
  • Patent number: 10255956
    Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Iwase, Ken Matsubara
  • Patent number: 10236041
    Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Thomas Kern, Christian Peters
  • Patent number: 10176874
    Abstract: A storage device includes bit lines including a first bit line and a second bit line, memory units including a first memory string having memory cells connected in series, connected to the first bit line, and a second memory string having memory cells connected in series, connected to the second bit line, word lines each connected in common to a gate of a memory cell in the first string and a gate of a memory cell in the second string, and a controller configured to control voltages applied to the bit lines and the word lines during writing. When writing is performed on a selected memory cell of the first memory string, a first voltage is applied to a selected word line connected to the gate of the selected memory cell while a second voltage higher than a zero voltage is applied to the first bit line.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomohiro Kuki, Yasuhiro Shimura
  • Patent number: 10157645
    Abstract: To obtain a booster circuit capable of reducing voltage stress applied to a booster cell, provided is a booster circuit including a plurality of booster cells connected in series. Each of the plurality of booster cells includes a charge transfer transistor connected between an input terminal and an output terminal, and a boost capacitor connected between the input terminal and a clock terminal. Among the plurality of booster cells, a plurality of booster cells at least in a last stage are connected in parallel so that the plurality of booster cells connected in parallel are connected to a booster cell in a previous stage of the last stage by switching the plurality of booster cells in the last stage in accordance with a boosting operation.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: ABLIC INC.
    Inventor: Makoto Mitani
  • Patent number: 10128248
    Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Karthik Ns, Dharmaray Nedalgi, Vani Deshpande, Leonhard Heiss, Amit Kumar Srivastava
  • Patent number: 10115441
    Abstract: A row decoder includes a plurality of address lines, a first selection circuit and a second selection circuit. The first selection circuit is coupled to the address lines and with a latch function, and configured to enable and latch a first selection signal to select a first word line in a first cell array. The second selection circuit is coupled to the address lines and without the latch function, and configured to enable a second selection signal to select a second word line in a second cell array.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: October 30, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shang-Chi Yang, Chun-Yu Liao
  • Patent number: 10115460
    Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cesare Torti, Fabio Enrico Carlo Disegni, Davide Manfreā€², Massimo Fidone
  • Patent number: 10056153
    Abstract: A semiconductor device according to an embodiment includes first and second memory cells, a first word line, and first and second bit lines. The first memory cell has a first gate electrode and a first channel. The second memory cell has a second gate electrode and a second channel. The first word line connected with each of the first and second gate electrodes. The first and second bit lines electrically connected with the first and second channels, respectively. The semiconductor device erases data of each of the first and second memory cells, and then shifts respective threshold voltages of the first and second memory cells while making a first voltage between the first gate electrode and the first channel, and a second voltage between the second gate electrode and the second channel. The first voltage is different from the second voltage.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Yusuke Umezawa
  • Patent number: 10056133
    Abstract: A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 21, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Guseul Baek, Toshikazu Fukuda
  • Patent number: 9997235
    Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei-Min Chan, Yen-Huei Chen
  • Patent number: 9991292
    Abstract: A driver includes a dummy stage and one or more additional stages coupled to the dummy stage. The dummy stage includes a first transistor coupled between an input terminal and an output terminal. The first transistor includes two electrodes forming at least a first capacitor to store at least a portion of static electricity received through the input terminal. The one or more additional stages output gate signals, which may be received, for example, by a display device.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaewon Kim, Boyeong Kim, Soo-Hyun Kim, Kyung-ho Park, HyungJun Park, Dong-Hyun Yoo, Ki Yeup Lee, Seongyoung Lee
  • Patent number: 9953870
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: April 24, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Patent number: 9940031
    Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Futatsuyama
  • Patent number: 9818489
    Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.
    Type: Grant
    Filed: February 4, 2017
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Nagai, Masami Hanyu, Yuka Suzuki
  • Patent number: 9805800
    Abstract: An EPROM device includes bit lines branching from a supply voltage line, a first group of enablement signal lines intersecting the bit lines, unit cells respectively located at cross points of the bit lines and the first group of enablement signal lines, pass transistors, load transistors, comparators, and enablement signal generators. One of the pass transistors and one of the load transistors are coupled in series between the supply voltage line and each of the bit lines. Each of the comparators receives voltages of both ends of any one of the load transistors to generate an output signal. Each of the enablement signal generators receives one of the output signals of the comparators and one of a second group of enablement signals and outputs one of a third group of enablement signals to turn off one of the pass transistors responsive to a program current reaching a reference value.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 31, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyun Min Song
  • Patent number: 9792994
    Abstract: A driver circuit, such as could be used as an off-chip driver for an I/O pin on a memory circuit, is presented. The driver has a PMOS connected between a supply level and the driver's output node. In an active mode, the bulk terminal of the PMOS is connected to the supply level; and in a standby mode, the PMOS's bulk terminal is set to a higher level. This reduces the leakage current through the PMOS in the standby mode, allowing for smaller device with a lower capacitance to be used.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Primit Modi, Venkatesh Ramachandra
  • Patent number: 9786340
    Abstract: A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 10, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 9779816
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 9747978
    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 29, 2017
    Assignee: INTEL CORPORATION
    Inventors: Balaji Srinivasan, Doyle Rivers, Derchang Kau, Matthew Goldman
  • Patent number: 9747997
    Abstract: A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 29, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jun Lee, Sang-Hyun Joo
  • Patent number: 9734785
    Abstract: Provided is a gate driving unit including: a plurality of stages configured to be activated sequentially so as to generate gate signals; and a plurality of repair blocks having sizes smaller than the corresponding stages and configured to repair defects of the stages. Each of the repair blocks is disposed proximate to two or more stages so as to be configured to repair defects in the two or more stages.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sehyoung Cho, Kyung-hoon Kim, Dongwoo Kim, Ilgon Kim, Meehye Jung, Kangmoon Jo
  • Patent number: 9704579
    Abstract: A non-volatile semiconductor memory device comprising a control circuit is provided, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined blocks of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word line in the edge part of the memory cell array.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 11, 2017
    Assignee: Powerchip Technology Corporation
    Inventor: Mathias Bayle
  • Patent number: 9685231
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 20, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Patent number: 9632868
    Abstract: An operating method of a storage device includes reading data from a nonvolatile memory using first read parameters and second read parameters and collecting read histories associated with a plurality of read operations. First histories and second histories are determined from the collected read histories. The second read parameters are adjusted according to the first histories, and the first read parameters are adjusted according to the second histories. The read histories include information on read voltages used to perform the read operations, and the first histories and the second histories are determined from the collected read histories according to the number of read voltages having the same level.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byungjune Song
  • Patent number: 9614533
    Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Fangxing Wei, Setul M Shah, Michael J Allen, Khushal N Chandan
  • Patent number: 9607702
    Abstract: A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of word lines between the first and second string select switches. A channel-side voltage can be applied to the channel lines. A control voltage can be applied to a selected subset of the first string select switches. The channel lines can be floated at ends of the second string select switches. Tunneling in memory cells coupled to an unselected subset of the first string select switches can be inhibited. Word line-side erase voltages can be applied to word lines in the set of word lines in the block to induce tunneling in memory cells coupled to the word lines and coupled to the selected subset of the first string select switches.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventor: Kuo-Pin Chang
  • Patent number: 9595337
    Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takashi Maeda
  • Patent number: 9557763
    Abstract: According to an embodiment, an electronic circuit is described comprising a processing circuit, a power supply configured to supply power to the processing circuit via two supply nodes; a determiner configured to determine whether the voltage between the two supply nodes is above a predetermined reference voltage; and a clock generator configured to generate a clock signal for the processing circuit wherein the clock generator is configured to if the determiner determines that the voltage between the two supply nodes is again, after pausing the generation of clock edges, above the predetermined threshold the clock generator generates a clock edge irrespective of whether it is currently a time point given by the predetermined periodicity.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies AG
    Inventor: Marco Bucci
  • Patent number: 9542993
    Abstract: In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 10, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Loren McLaury
  • Patent number: RE47017
    Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Nakano, Mikio Ogawa
  • Patent number: RE48013
    Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Bum Kim, Hyung Gon Kim, Chul Ho Lee, Hong Seok Chang