Drive Circuitry (e.g., Word Line Driver) Patents (Class 365/185.23)
  • Patent number: 11943922
    Abstract: A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.
    Type: Grant
    Filed: November 11, 2023
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guangyuan Li, Qinghua Zhao, Sudarshan Narayanan, Yuji Totoki, Fumiaki Toyama
  • Patent number: 11942157
    Abstract: An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: March 26, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang, Xiaochen Zhu
  • Patent number: 11915762
    Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Dong Hun Kwak, Hyung Jin Choi
  • Patent number: 11915756
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 27, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Patent number: 11901010
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vinh Q. Diep, Ching-Huang Lu, Yingda Dong
  • Patent number: 11894056
    Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 6, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Shiqian Shao, Fumiaki Toyama
  • Patent number: 11875862
    Abstract: A memory device may include a first set of word lines in a first zone and a second set of word lines in a second zone. When programming memory cells coupled to a first target word line of the first set of word lines, a first pass voltage may be applied to at least one word line of the first set of word lines. When programming memory cells coupled to a second target word line of the second set of word lines, a second pass voltage may be applied to at least one word line of the second set of word lines. The at least one word line of the first set of word lines and the at least one word line of the second set of word lines have been programmed. The second pass voltage may be higher than the first pass voltage.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: January 16, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yali Song, XiangNan Zhao, Ying Cui
  • Patent number: 11875863
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The memory cells may be coupled to a plurality of word lines. The peripheral circuit may perform a memory operation on selected memory cells. The control logic may control the peripheral circuit, during the memory operation, to apply an operating voltage to a selected word line, among the plurality of word lines, coupled to the selected memory cells, a first pass voltage to target word lines adjacent to the selected word line among unselected word lines, based on whether the operating voltage is lower than or equal to a reference voltage, and a second pass voltage, having a lower level than the first pass voltage, to remaining unselected word lines, other than the target word lines.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Moon Sik Seo
  • Patent number: 11853207
    Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 11842766
    Abstract: Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (?) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: December 12, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Rumin Ji
  • Patent number: 11837313
    Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Chulmin Jung
  • Patent number: 11823742
    Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mark A Helm, Joseph T. Pawlowski
  • Patent number: 11817150
    Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: November 14, 2023
    Assignee: Sandisk Technologies LLC
    Inventors: Shiqian Shao, Fumiaki Toyama
  • Patent number: 11798638
    Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 24, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Kou Tei, Ohwon Kwon
  • Patent number: 11791804
    Abstract: Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 17, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhonglai Liu
  • Patent number: 11790984
    Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: October 17, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Nimrod Bregman, Ofir Kanter
  • Patent number: 11790991
    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
  • Patent number: 11742025
    Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array including a plurality of memory cells; a first local signal line decoder coupled to the memory array; a second local signal line decoder coupled to the memory array; and a controller coupled to and controlling the memory array, the first local signal line decoder and the second local signal line decoder, wherein in programming, a threshold voltage distribution of the memory cells is lower than a read voltage; and in erase, the threshold voltage distribution of the memory cells is higher than the read voltage.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 11742035
    Abstract: A memory device may include a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform a program verify operation for a target program state among a plurality of program states on selected memory cells among the plurality of memory cells. The control logic is configured to control the peripheral circuit to precharge bit lines coupled to first memory cells among the selected memory cells and bit lines coupled to second memory cells among the selected memory cells in the program verify operation. The first memory cells are program-passed memory cells among memory cells programmed to a program state higher than the target program state among the plurality of program states. The second memory cells are memory cells programmed to a program state lower than or equal to the target program state among the plurality of program states.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 29, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11727993
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11726142
    Abstract: An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: August 15, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Pin Lin, Lien-Hsiang Sung
  • Patent number: 11727989
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: August 15, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 11728000
    Abstract: A system for testing memory includes logic that is configured to perform various normal memory operations (e.g., erase, read and write operations) on a memory device and to determine operational parameters associated with the memory operations. As an example, the amount of time to perform one or more memory operations may be measured, a number of errors resulting from the memory operations may be determined, or a number of memory cells storing noisy bits may be identified. One or more of the operational parameters may then be analyzed to determine whether they are in a range expected for counterfeit or defective memory. If so, the logic determines that the memory under test is counterfeit or defective and provides a notification about such determination.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 15, 2023
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventors: Biswajit Ray, Umeshwarnath Surendranathan, Preeti Kumari, Md Raquibuzzaman
  • Patent number: 11715537
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 1, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 11698725
    Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
  • Patent number: 11699487
    Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and configured to transmit a boosting prevention voltage to a channel region in the cell string while applying an equalizing voltage to the word lines.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: July 11, 2023
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 11670374
    Abstract: Some embodiments include apparatuses and methods using first and second data lines coupled to respective first and second memory cell strings; an access line shared by first and second memory cells of the first and second memory cell strings, respectively; and a control unit including circuitry to perform operations including charging the first data line to a first voltage during a first time interval of an operation performed on first and second memory cells; holding the second data line at a second voltage during the first time interval; charging the first data line to a third voltage during a second time interval of the operation; charging the second data line to a fourth voltage during the second time interval; and determining, during the second time interval of the operation, whether the first memory cell reaches a first threshold voltage and whether the second memory cell reaches a second threshold voltage.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 11653488
    Abstract: An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Litao Yang, Srinivas Pulugurtha, Haitao Liu
  • Patent number: 11646089
    Abstract: A memory device includes a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit programs the plurality of memory cells to a program state among a plurality of program states. The control logic controls the peripheral circuit to perform a program verify operation for at least one program state among the plurality of program states, counts a bit number having a predetermined logic value by comparing a program verify voltage corresponding to a target program state in the at least one program state in a program verify operation for the target program state with threshold voltages of the plurality of memory cells, and determines a start time of a program verify operation for a program state higher than the target program state among the plurality of program states, based on the bit number having the predetermined logic value.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11600345
    Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller may sense a first threshold voltage of the selected memory cell. In response to the sensed first threshold voltage being between a first pre-program verify level and a first program verify level, the controller may bias the selected memory cell for SSPC programming. The first pre-program verify level might be less than a final pre-program verify level and the first program verify level might be less than a final program verify level. In response to the sensed first threshold voltage being less than the first pre-program verify level, the controller may bias the selected memory cell for non-SSPC programming. In response to the sensed first threshold voltage being greater than the first program verify level, the controller may inhibit programming of the selected memory cell.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Ankit Sharma
  • Patent number: 11600327
    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Kenrou Kikuchi, Yasuhiro Shimura
  • Patent number: 11594283
    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: February 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Taeck Jung, Sang-Wan Nam, Jinwoo Park, Jaeyong Jeong
  • Patent number: 11581297
    Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: February 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghyuk Choi, Bongsoon Lim, Hongsoo Jeon, Jaeduk Yu
  • Patent number: 11568948
    Abstract: A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Chang, Gu-Huan Li, Shao-Yu Chou
  • Patent number: 11557965
    Abstract: A semiconductor device comprises: a voltage generator suitable to pump a power source voltage to generate a first pumping voltage in response to an operation clock, a clock generator suitable to generate the operation clock having a first frequency during an initial operation period in which a level of the first pumping voltage is at a first level and to generate the operation clock having a second frequency after the initial operation period, the second frequency generated to be lower than the first frequency in response to a rise in a level of the first pumping voltage to a second level greater than the first level, and an internal circuit suitable to perform a predetermined internal operation in response to the first pumping voltage.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 17, 2023
    Assignee: SK hynix Inc.
    Inventor: Seok In Hong
  • Patent number: 11538529
    Abstract: Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Guanglei An, Qiang Tang
  • Patent number: 11532258
    Abstract: A display device for displaying an image, includes: a data line driver which includes a buffer configured to supply a reference voltage to a load including pixels and a boost circuit configured to supply a charging voltage to the load including the pixels; and a calibration unit which controls the boost circuit to supply the charging voltage to the load for a driving time and controls the driving time according to a difference between a target voltage and a voltage formed after charge sharing is performed in the load to which the charging voltage is supplied.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: December 20, 2022
    Assignee: Anapass Inc.
    Inventors: Joon Bae Park, Jun Young Jang, Hyun Seung Lee, Dong Joon Lee
  • Patent number: 11532350
    Abstract: A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Insung Koh
  • Patent number: 11527286
    Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Nathan Joseph Sirocka, Hari Giduturi
  • Patent number: 11514973
    Abstract: A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woojin Rim, Yongho Kim, Hoonki Kim
  • Patent number: 11514976
    Abstract: The present technology includes a memory device which includes a plurality of planes in which data is stored, a peripheral circuit configured to perform operations on the plurality of planes, micro-control circuits configured to control the peripheral circuit so that the operations on the plurality of planes are independently performed, and a memory manager including a control memory in which different control codes for controlling the peripheral circuit are stored, and configured to output the control codes to the micro-control circuits, wherein the memory manager is configured to sequentially output a selected control code among the control codes to the micro-control circuits respectively corresponding to the planes.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Hyun Chung
  • Patent number: 11508449
    Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 22, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ching-Huang Lu, Vinh Q. Diep, Zhengyi Zhang, Yingda Dong
  • Patent number: 11508448
    Abstract: A memory system including a memory device suitable for performing, in stages, a program loop including a program operation and a program verification operation on each page within a memory block selected among a plurality of memory blocks, updating a maximum number of program loops for the selected memory block by comparing a number of program loops on each page, which are performed until the program verification operation is processed as a pass on the page, with a current maximum number of program loops for the selected memory block, and storing the updated maximum number of program loops for the selected memory block as program pass information of the selected memory block; and a controller suitable for managing the selected memory block as a bad block based on the program pass information of the selected memory block.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Won Jin Jung
  • Patent number: 11500446
    Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.
    Type: Grant
    Filed: September 28, 2019
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Richard Fastow, Shankar Natarajan, Chang Wan Ha, Chee Law, Khaled Hasnat, Chuan Lin, Shafqat Ahmed
  • Patent number: 11501821
    Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: November 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Ken Oowada, Mitsuteru Mushiga
  • Patent number: 11495312
    Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 8, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Wen-Chiao Ho, Pil-Sang Ryoo
  • Patent number: 11494116
    Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a central processing unit configured to output a read command for checking an erase state of a selected storage region in response to a program request from a host, determine the number of dummy pages according to the erase state, and output a program command according to the number of dummy pages; and a memory interface configured to, when user data corresponding to the program request is output to the selected storage region, selectively generate dummy data corresponding to the number of dummy pages, and output the dummy data with the user data.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Se Chang Park
  • Patent number: 11488657
    Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 1, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jen-Hung Huang, Han-Sung Chen
  • Patent number: 11468949
    Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 11, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Pitamber Shukla, Giuseppina Puzzilli, Niccolo′ Righetti, Scott A. Stoller, Priya Venkataraman
  • Patent number: 11437110
    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Deepanshu Dutta, Huai-Yuan Tseng