Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

Abstract: To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage, applying a verify voltage to a selected word line that is coupled to the selected memory cells, and discharging the selected bit lines that are coupled to on-cells over a first time interval. The method also includes sensing a sensed voltage level on a selected bit line, loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level, and repeating the operations of sensing and loading for each of the selected bit lines.

Abstract: An storage device is provided. The storage device includes: a nonvolatile memory; and at least one processor configured to: obtain an input symbol to be stored in a target memory cell among a plurality of memory cells of the nonvolatile memory; obtain cell features of the plurality of memory cells; determine a target voltage for the target memory cell based on the input symbol and the cell features of the plurality of memory cells; and provide the target voltage to the target memory cell.

Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. The circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. The circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a Pearson detector, and determine the originally programmed data of the codeword using the Pearson detector.

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

Abstract: A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.

Abstract: A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is coupled to the word lines and bit lines and is configured to apply an unselected top voltage to unselected ones of the top drain-side select gate transistors during a memory operation. The control means is also configured to simultaneously apply a selected top voltage to selected ones top drain-side select gate transistors during the memory operation. The unselected top voltage is intentionally different electrically than the selected top voltage.

Abstract: A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to the second wordline, re-read and store the first data from the first wordline in a second location during the programming, compare the read first data and the re-read first data, and mark one or more bits of the first wordline that are different based on the comparing. The marked one or more bits are used as soft bits in future read and decode operations.

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

Abstract: The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918).

Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract: A processing device receives a command to arm a memory device for self-destruction. In response to the command, a self-destruction countdown timer is commenced. An expiry of the self-destruction countdown timer and based on detecting the expiry of the self-destruction countdown timer, data stored by the memory device is destructed.

Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.

Abstract: Data blocks may be optimized and managed in a mixed mode that utilizes a single-level cell (SLC) mode in combination with higher-density memory modes to promote full block utilization and to increase overall cycles of the data blocks. A data block cycling process in the mixed mode can place a data block in a higher-density memory mode that includes a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode, if the SLC cycle count of the data block is relatively higher as compared to other data blocks. Similarly, in the mixed mode, a data block may be placed in the SLC mode to store parity data or intermediate data if the corresponding TLC cycle count is relatively higher than other data blocks. Data clocks cycles may also be evenly distributed in the mixed mode, thereby balancing the mixed mode usage across all data blocks.

Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.

Abstract: An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.

Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.

Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.

Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

Abstract: A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.

Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.

Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.

Abstract: Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks.

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

Abstract: A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.

Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.

Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: Various aspects relate to a threshold switch structure and a use of such threshold switch structure as a threshold switch in a memory cell arrangement, the threshold switch structure including: a first electrode, a second electrode, a switch element in direct physical contact with the first electrode and the second electrode, the switch element including a layer of a spontaneously polarizable material. The first electrode, the second electrode, and the switch element are configured to allow for a switching of the switch element between a first electrical conductance state and a second electrical conductance state as a function of a voltage drop provided over the switch element by the first electrode and the second electrode.