Threshold Setting (e.g., Conditioning) Patents (Class 365/185.24)
  • Patent number: 11942150
    Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng
  • Patent number: 11941283
    Abstract: A processing device receives a command to arm a memory device for self-destruction. In response to the command, a self-destruction countdown timer is commenced. An expiry of the self-destruction countdown timer and based on detecting the expiry of the self-destruction countdown timer, data stored by the memory device is destructed.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Robert W. Strong
  • Patent number: 11934675
    Abstract: Data blocks may be optimized and managed in a mixed mode that utilizes a single-level cell (SLC) mode in combination with higher-density memory modes to promote full block utilization and to increase overall cycles of the data blocks. A data block cycling process in the mixed mode can place a data block in a higher-density memory mode that includes a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode, if the SLC cycle count of the data block is relatively higher as compared to other data blocks. Similarly, in the mixed mode, a data block may be placed in the SLC mode to store parity data or intermediate data if the corresponding TLC cycle count is relatively higher than other data blocks. Data clocks cycles may also be evenly distributed in the mixed mode, thereby balancing the mixed mode usage across all data blocks.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Sourabh Sankule
  • Patent number: 11922041
    Abstract: An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Steven Michael Kientz, Chia-Yu Kuo
  • Patent number: 11923028
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: March 5, 2024
    Inventors: Chenrong Xiong, Jie Chen
  • Patent number: 11916058
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11894077
    Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 6, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ke Zhang, Minna Li, Liang Li
  • Patent number: 11887671
    Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Joohyun Jin, Chao Zhang
  • Patent number: 11887674
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: January 30, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanjie Wang, Guirong Liang, Xiaoyu Che, Yi Song
  • Patent number: 11887669
    Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11887681
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Rayaprolu, Ashutosh Malshe, Gary Besinga, Roy Leonard
  • Patent number: 11886736
    Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Guang Hu
  • Patent number: 11881284
    Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu, Jiangli Zhu
  • Patent number: 11868647
    Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngdeok Seo, Jinyoung Kim, Sehwan Park, Ilhan Park
  • Patent number: 11869582
    Abstract: A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoon Park, Sungwon Yun, Hyunjun Yoon, Wontaeck Jung
  • Patent number: 11810625
    Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Seagate Technology LLC
    Inventors: Ryan J. Goss, Christopher A. Smith, Indrajit Zagade, Jonathan Henze
  • Patent number: 11798628
    Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Masaru Yano, Toshiaki Takeshita
  • Patent number: 11798626
    Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chaehoon Kim, Junyoung Ko, Sangwan Nam, Minjae Seo, Jiwon Seo, Hojun Lee
  • Patent number: 11776643
    Abstract: Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: October 3, 2023
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 11763914
    Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
  • Patent number: 11756620
    Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 12, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 11756645
    Abstract: A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung-Ying Lee, Jin Cai
  • Patent number: 11749350
    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
  • Patent number: 11720283
    Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: August 8, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Judah Gamliel Hahn
  • Patent number: 11715534
    Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventors: Rieko Funatsuki, Takashi Maeda, Reiko Sumi, Reika Tanaka, Masumi Saitoh
  • Patent number: 11710527
    Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Patent number: 11651821
    Abstract: A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 16, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nikhil Arora, Lovleen Arora
  • Patent number: 11651824
    Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Yeong Jo Mun
  • Patent number: 11636904
    Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yoav Weinberg, Eric N. Lee
  • Patent number: 11630722
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: April 18, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guangming Lu, Kent D. Anderson, Anantha Raman Krishnan, Shafa Dahandeh
  • Patent number: 11615851
    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 28, 2023
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
  • Patent number: 11610632
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Patent number: 11605435
    Abstract: Various aspects relate to a threshold switch structure and a use of such threshold switch structure as a threshold switch in a memory cell arrangement, the threshold switch structure including: a first electrode, a second electrode, a switch element in direct physical contact with the first electrode and the second electrode, the switch element including a layer of a spontaneously polarizable material. The first electrode, the second electrode, and the switch element are configured to allow for a switching of the switch element between a first electrical conductance state and a second electrical conductance state as a function of a voltage drop provided over the switch element by the first electrode and the second electrode.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 14, 2023
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Tony Schenk
  • Patent number: 11600339
    Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 7, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Chieh Cheng, Chun-Chang Lu, Wen-Jer Tsai
  • Patent number: 11594292
    Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott A. Stoller, Pitamber Shukla, Kishore Kumar Muchherla, Fulvio Rori, Bin Wang
  • Patent number: 11587638
    Abstract: A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 11581052
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Akiyoshi Hashimoto, Makoto Kuribara, Takeshi Tomizawa, Katsuhiko Ueki
  • Patent number: 11574693
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 7, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Chin-Yi Chen, Muhammad Masuduzzaman, Dengtao Zhao, Anubhav Khandelwal, Ravi Kumar
  • Patent number: 11562793
    Abstract: A memory sub-system configured to read soft bit data by adjusting the read voltage applied to read hard bit data from memory cells. For example, in response to a read command identifying a group of memory cells, a memory device is to: read the group of memory cells using a first voltage to generate hard bit data indicating statuses of the memory cells subjected to the first voltage; change (e.g., through boosted modulation) the first voltage, currently being applied to the group of memory cells, to a second voltage and then to a third voltage; reading the group of memory cells at the second voltage and at the third voltage to generate soft bit data (e.g., via an exclusive or (XOR) of the results of reading the group of memory cells at the second voltage and at the third voltage).
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 11557358
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta, Ravi Kumar
  • Patent number: 11538525
    Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: December 27, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
  • Patent number: 11537326
    Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Uri Peltz, Karin Inbar
  • Patent number: 11538829
    Abstract: A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 27, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Erh-Kun Lai
  • Patent number: 11521700
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 6, 2022
    Assignee: INNOGRIT TECHNOLOGIES co., LTD.
    Inventors: Chenrong Xiong, Jie Chen
  • Patent number: 11498326
    Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. A memory component stores memory values associated with the print component, and a control circuit, in response to a sequence of operating signals on the I/O pads representing a memory read, provides an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 15, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Michael Gardner, Boon Bing Ng
  • Patent number: 11495294
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
  • Patent number: 11494084
    Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 8, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sheyang Ning, Lawrence Miranda
  • Patent number: 11488684
    Abstract: A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ran Zamir, Alexander Bazarsky
  • Patent number: 11488666
    Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: November 1, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11467745
    Abstract: A memory controller, for controlling a memory device including a plurality of memory blocks, includes a garbage collection controller configured to determine candidate blocks in which valid data is equal to or less than a predetermined ratio among the plurality of memory blocks, and configured to determine at least two or more memory blocks as victim blocks among the candidate blocks based on information on blocks that may be simultaneously erased among the plurality of memory blocks. The memory controller also includes an operation controller configured to control the memory device to copy valid data stored in the victim blocks to a different memory block.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 11, 2022
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong