Threshold Setting (e.g., Conditioning) Patents (Class 365/185.24)
  • Patent number: 11410732
    Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
  • Patent number: 11410711
    Abstract: The present application is applicable to the field of integrated circuit technology, and provides a data writing method, system, apparatus, device and medium for an integrated circuit chip. The data writing method is applied to a writer, the integrated circuit chip is electrically connected with the writer through a power-supply positive terminal and a power-supply negative terminal, and the data writing method includes: sending a data writing order to the integrated circuit chip, where the data writing order is configured to instruct the integrated circuit chip to enter a data writing mode after receiving the data writing order; and performing data writing to the integrated circuit chip by controlling an electrical parameter of an input voltage of the power-supply positive terminal or the power-supply negative terminal of the integrated circuit chip after the integrated circuit chip enters the data writing mode.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 9, 2022
    Assignee: TIRO INNOVATION TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventor: Weixing Zhu
  • Patent number: 11393541
    Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Patent number: 11380371
    Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Yu-Der Chih
  • Patent number: 11373712
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including determining first values of a metric that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory device. The operations further include determining second values of the metric based on the first values, and adjusting valley margins of the memory cell in accordance with the second values of the metric.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
  • Patent number: 11366592
    Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Gary F. Besigna
  • Patent number: 11355204
    Abstract: Techniques related to methods and systems for improving a performance related to reading data stored in memory cells. The method includes selecting a first voltage read range and a second voltage read range from multiple voltage read ranges that are associated with a number of bits storable in a memory cell. The method includes receiving, a first set of parameters that represent a first probability distribution of first candidate voltage read thresholds within the first voltage read range. The method includes receiving a second set of parameters that represent a second probability distribution of second candidate voltage read thresholds within the second voltage read range. The method includes generating, based on an input to an objective function, a voltage read threshold. The method includes reading data stored in the memory cell based on the voltage read threshold.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Haobo Wang, Fan Zhang
  • Patent number: 11354098
    Abstract: The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 7, 2022
    Assignee: SYNERGER INC.
    Inventor: Lee Wang
  • Patent number: 11342044
    Abstract: System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 24, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ziv Hershman, Ilan Margalit, Avraham Fishman
  • Patent number: 11335413
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 17, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 11335420
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes memory cells connected between a bit line and a source line, a voltage generator for generating program voltages and verify voltages which are to be applied to a selected word line connected to a selected memory cell, a page buffer for storing data respectively sensed in verify operations using the verify voltages, and for transferring a program allow voltage, a program inhibit voltage or a program control voltage to the bit line by sequentially using the data, and a logic circuit for generating page buffer control signals for controlling the page buffer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventor: Soo Yeol Chai
  • Patent number: 11302394
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 12, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu
  • Patent number: 11276465
    Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Mase J. Taub, DerChang Kau
  • Patent number: 11237726
    Abstract: A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien, Violante Moschiano
  • Patent number: 11232842
    Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elisha Halperin, Evgeny Blaichman, Amit Berman
  • Patent number: 11222694
    Abstract: A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: January 11, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Sirisha Bhamidipati, Arka Ganguly, Ohwon Kwon, Chia-Kai Chou, Kou Tei
  • Patent number: 11217320
    Abstract: A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Mustafa N. Kaynak, Steven Michael Kientz
  • Patent number: 11158363
    Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato
  • Patent number: 11087815
    Abstract: Readout circuit and magnetic memory are provided. The readout circuit includes a first charging capacitor with one end grounded and another end coupled to an output of a data unit; a first pre-charge module for charging the first charging capacitor; a first discharge control module for controlling a magnitude of a data voltage; a second charging capacitor with one end grounded and another end coupled to an output of a reference unit; a second pre-charge module for charging the second charging capacitor; a second discharge control module for controlling a magnitude of a reference voltage; and a sense amplifier for outputting readout signals.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 10, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Siwen Zheng, Hao Ni, Tengye Wang, Tao Wang
  • Patent number: 11056172
    Abstract: A flash memory and an operation method thereof are provided. The flash memory includes a plurality of memory cell strings and a pass voltage generator. Each of the memory cell strings includes a plurality of memory cells. The pass voltage generator is configured to provide a pass voltage to a plurality of word lines of a plurality of unselected memory cells of a selected memory string. During a reading operation, the pass voltage generator raises the pass voltage from a first voltage at a first time point, and raises the pass voltage to a second voltage at a second time point. The second voltage is lower than a target voltage times a preset ratio The first time point is earlier than a start time point of a bit line voltage received by the selected memory cell, and the second time point occurs at the start time point of the bit line voltage.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Che-Ping Chen, Ya-Jui Lee, Shin-Jang Shen, Yih-Shan Yang
  • Patent number: 11043275
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first word line including a plurality of first cells and a second word line adjacent to the first word line and including a plurality of second cells. The memory controller determines a read voltage to be used with respect to the plurality of the first cells, according to a plurality of adjacent voltages representing respective threshold voltages of the plurality of the second cells. The memory controller reads data from the first word line using a plurality of determined read voltages.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Itoh, Tomoya Kodama
  • Patent number: 11031089
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
  • Patent number: 10998064
    Abstract: A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Crossbar, Inc.
    Inventors: Jeremy Guy, Sung Hyun Jo, Hagop Nazarian, Ruchirkumar Shah, Liang Zhao
  • Patent number: 10976936
    Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
  • Patent number: 10964396
    Abstract: A semiconductor memory device includes first and second bit lines, first and second memory transistors connected to the respective first and second bit lines, a source line connected to the first and second memory transistors, and a word line connected to gate electrodes of the first and second memory transistors. In an erase operation that erases data in the first and second memory transistors: a first erase voltage application operation is performed; an erase verify operation is performed on only one of the first and second memory transistors; and a second erase voltage application operation is performed without performing the erase verify operation on another of the first and second memory transistors.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshikazu Harada
  • Patent number: 10964400
    Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10929309
    Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 23, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Alon Marcu, Ariel Navon
  • Patent number: 10921989
    Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
  • Patent number: 10916312
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroyuki Nagashima
  • Patent number: 10910064
    Abstract: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Kwang-Ho Kim, Masaaki Higashitani
  • Patent number: 10878910
    Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Steve Kientz, Bruce A. Liikanen
  • Patent number: 10878919
    Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Ho Cho, Kyo Man Kang, Dae Seok Byeon, Jung Ho Song, Chi Weon Yoon
  • Patent number: 10878905
    Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 29, 2020
    Assignee: Microchip Technology Inc.
    Inventors: John L. McCollum, Fengliang Xue
  • Patent number: 10861544
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condition is selected for the RRAM cell, based on the cell characteristic. The RRAM cell is written to, using the selected write condition.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 8, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu
  • Patent number: 10803954
    Abstract: A memory system includes a memory unit with a plurality of first memory cells connected to a first word line and a memory controller to control the memory unit to write data in page units equal in size to the number of first memory cells. The memory unit is configured to write a plurality of pages of data to the plurality of first memory cells and then read each page of data thus written. The memory controller determines whether or not each page of data, as read from the plurality of first memory cells, satisfies a predetermined condition, and registers a determination result for each page indicating whether the predetermined condition was satisfied.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kiwamu Watanabe
  • Patent number: 10784275
    Abstract: A nonvolatile semiconductor storage device includes a memory cell array layer that includes a plurality of nonvolatile memory cells connected in series in a vertical direction above a semiconductor substrate, a plurality of word lines respectively connected to gates of the plurality of nonvolatile memory cells, a select gate transistor layer that is located above the memory cell array and includes at least first and second select gate transistors connected in series in the vertical direction and to the plurality of nonvolatile memory cells, and at least first and second select gate lines respectively connected to the at least first and second select gate transistors, and a control circuit configured to execute a read operation on the nonvolatile memory cells, such that during a read period of the read operation, signals having different voltage levels are supplied to the at least first and second select gate lines.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10777278
    Abstract: Provided are a non-volatile memory device and an erasing method thereof. The erasing method of the non-volatile memory device including a plurality of cell strings in which memory cells and selection transistors are connected, includes: performing a first erase operation based on an erase voltage provided to a first electrode of at least one of the selection transistors and an erase control voltage provided to a second electrode of the at least one of the selection transistors; determining whether there are slow erase cells by performing a multiple erase verify operation based on first and second verify voltages, the second verify voltage being higher than the first verify voltage; adjusting, when there are slow erase cells, the erase control voltage such that a voltage difference between the erase voltage and the erase control voltage increases; and performing a second erase operation based on the adjusted erase control voltage.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Lee, Young-sik Rho, Il-han Park
  • Patent number: 10777277
    Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
  • Patent number: 10750260
    Abstract: A ZR or ZR+ interface includes circuitry configured to receive one or more client signals; and circuitry configured to transmit the one or more client signals as an aggregate signal in a Flexible Ethernet (FlexE) format in one of a ZR format and a ZR+ format, including a mapping indicative of how the one or more client signals are one of multiplexed and subrated into the aggregate signal. The aggregate signal can have a rate that does not correspond to a standard Ethernet Physical Medium Dependent (PMD). The FlexE format can include a plurality of FlexE instances with at least one of the FlexE instances having calendar slots removed for a subrating application.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 18, 2020
    Assignee: Ciena Corporation
    Inventor: Sebastien Gareau
  • Patent number: 10734057
    Abstract: Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 10720220
    Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiko Kamata, Yoko Deguchi, Takuyo Kodama, Tsukasa Kobayashi, Mario Sako, Kosuke Yanagidaira
  • Patent number: 10658031
    Abstract: To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.
    Type: Grant
    Filed: August 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Nagase
  • Patent number: 10607707
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Noboru Shibata, Hironori Uchikawa
  • Patent number: 10586596
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 10, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 10559369
    Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sebastien Andre Jean, Harish Reddy Singidi
  • Patent number: 10535671
    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
  • Patent number: 10521339
    Abstract: A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells; searching for a selected retired group of memory cells that can store a representation of the data unit without being erased; and writing the representation of the data unit to the selected retired group of memory cells.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 31, 2019
    Assignee: Technion Research and Development Foundation LTD.
    Inventors: Yitzhak Birk, Amit Berman
  • Patent number: 10521287
    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Seagate Technology LLC
    Inventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
  • Patent number: 10503586
    Abstract: Apparatuses, systems, and methods are disclosed for dynamic read operations. An on-die controller monitors one or more read statistics during a read operation for data of a non-volatile memory die. An on-die controller determines whether one or more read statistics satisfy a threshold for a read operation. An on-die controller dynamically modifies a read operation based on determining that one or more read statistics fail to satisfy a threshold.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 10, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Edgar Barber, Alex Bazarsky, Ariel Navon, Gadi Vishne, Joshua Lehmann, Judah Gamliel Hahn
  • Patent number: 10497460
    Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Hyun-Chul Yoon