Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Abstract: A nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of memory cells and a program control logic circuit controlling the memory cell array. The program control logic circuit programs a first memory cell so that the threshold voltage of the first memory cell corresponding to data of erasure state is higher than the threshold voltage of a second memory cell corresponding to data of program state, in the memory cell array. The nonvolatile memory device controlled in this manner can provide higher reliability.

Abstract: Technologies are generally described herein for performing a pulse programming operation on memory cells. The memory cells may be programmed according to a relative ranking of a property of the memory cells. The relative ranking may correspond to a particular word to be written to the memory cells. The memory cells may be pulsed until the property corresponds to a particular relative ranking. Some examples of properties of the memory cells include, but are not limited to, threshold voltages, resistance values, or current carrying capabilities.

Abstract: According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data.

Abstract: A read module reads memory cells along a first word line by applying a plurality of threshold voltages to the first word line; generates first information about a first memory cell located along the first word line and a first bit line indicating a location of a threshold voltage distribution of the first memory cell relative to the plurality of threshold voltages; reads a second memory cell located along the first word line, a second word line near the first word line, or a second bit line near the first bit line; and generates second information about the second memory cell indicating a state of the second memory cell causing interference to the first memory cell. A compensation module compensates for the interference by assigning one or more of a log-likelihood ratio and a hard decision to the first memory cells based on the first information and the second information.

Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

Abstract: A bias voltage generator for providing a control voltage and a source line voltage to a memory array includes a reference voltage generating circuit and a voltage converting circuit. The reference voltage generating circuit receives a program signal or an erase signal, and generates a reference voltage. If the program signal is received by the reference voltage generating circuit, the reference voltage has a positive temperature coefficient. If the erase signal is received by the reference voltage generating circuit, the reference voltage has a negative temperature coefficient. The voltage converting circuit converts the reference voltage into the control voltage and the source line voltage. The voltage converting circuit enlarges the reference voltage by a first magnification so as to produce the source line voltage, and enlarges the reference voltage by a second magnification so as to produce the control voltage.

Abstract: A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Abstract: The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program voltage applying operation, a first verifying operation, and a detrap voltage applying operation with respect to the plurality of memory cells, and a control logic unit configured to issue at least one command to the peripheral circuit unit to determine whether to perform the detrap voltage applying operation based on a result of the first verifying operation performed following the performance of the program voltage applying operation.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: An apparatus including a memory array and control circuitry. The control circuitry is configured to, based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges. The control circuitry is further configured to, based at least on the number of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage. The control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the estimated offset amount.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store.

Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.

Abstract: A double patterning layout design method includes defining critical paths including a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout includes anchoring the critical paths on the schematic circuit.

Abstract: The present invention provides a microcomputer having a CPU, a flash ROM which stores programs or the like therein and a read controller which controls reading of the flash ROM. In the microcomputer, the flash ROM is partitioned by sectors. When a read address is designated, the flash ROM outputs read data and security information for a sector corresponding to the read address. On the other hand, the read controller includes a switch which sets whether the flash ROM is of a boot device. When the flash ROM is undesignated as the boot device and the read data is protected by the security information, the read controller stops the output of the read data.

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.

Abstract: A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.

Abstract: A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Abstract: A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor coupled to an odd drain selection line or an even drain selection line, memory cells coupled to word lines, and a source selection transistor coupled to an odd source selection line or an even source selection line, page buffers suitable for storing data, a selection switch unit suitable for transferring the data stored in the page buffers or various voltages supplied from an external source to the bit lines and the source lines; and a control circuit suitable for controlling the page buffers and the selection switch unit.

Abstract: An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage cells is satisfied. A method includes performing a default erase operation for the one or more storage cells in response to determining that the use threshold is not satisfied. A method includes performing an extended erase operation for the one or more storage cells in response to determining that the use threshold is satisfied. An extended erase operation may include a greater number of erase pulse iterations than a default erase operation.

Abstract: A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics.

Abstract: Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be used to simultaneously sense two different threshold voltages. However, there may be variances in the threshold voltage shift of memory cells when read with a different bias condition than was used to verify. In one embodiment each programmed state is read using both (or all) bias conditions that were used during SMT verify. In other words, two (or more) different sense operations are used to read each memory cell. The data from these different sense operations may be used to compute initialization values (e.g., LLRs, LRs, probabilities) for an ECC decoder. In one embodiment, this technique is only performed when a normal read fails.

Abstract: A method of driving a nonvolatile memory device, includes; forward shifting threshold voltages of nonvolatile memory cells by executing a first program loop with respect to the nonvolatile memory cells, and thereafter, reverse shifting the threshold voltages of the nonvolatile memory cells, and again forward shifting the threshold voltages of the nonvolatile memory cells by executing a second program loop with respect to the nonvolatile memory cells.

Abstract: A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold.

Abstract: A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of memory cells, performing the read operation repetitively with changing levels of the read voltage according to the supplying condition of the read voltage in the event that the number of error bits in a data read from the memory cells exceeds an allowable range, and storing an iteration number of the read operation in the internal register in case the number of the error bits falls within the allowable range.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

Abstract: A memory device includes a memory array, an array gap, a voltage provider, and a voltage divider. The voltage provider is disposed in the array gap and coupled to a column of memory cells of the memory array for providing a first voltage to the column of memory cells when a memory cell of the column is selected at a write cycle. The voltage provider is coupled to the voltage provider and the column of memory cells for providing a second voltage lower than the first voltage to the column of memory cells when the memory of the column is half selected at the write cycle.

Abstract: Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

Abstract: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.

Abstract: A method of operating a semiconductor device includes storing LSB data in a LSB page included in plural pages of corresponding word line group of a first memory block, generating a data combination signal by combining plural sets of LSB data after the step of storing LSB data, storing the data combination signal in a second memory block, and storing MSB data in a MSB page included in the plural pages.

Abstract: Apparatuses, systems, and methods are disclosed for a read operation for a non-volatile memory. A method includes determining whether one or more non-volatile storage cells satisfy a predefined condition. A method includes preparing the one or more non-volatile storage cells for use prior to satisfying a read request from a storage client using the one or more non-volatile storage cells in response to determining that a predefined condition is satisfied.

Abstract: A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.

Abstract: A low-current FN channel for Erase, Program, Program-Inhibit and Read operations is disclosed for any non-volatile memory using FN-tunneling scheme for program and erase operation, regardless NAND, NOR, and EEPROM and regardless PMOS or NMOS non-volatile cell type. As a result, all above NMV memories can use the disclosed LV, compact PGM buffer to replace the traditional HV PGM buffer for saving in the silicon area and power consumption. The page buffer is used to store new loaded data for new writing and to convert the stored data into the required BL HV voltage for either Erase or Program operations according to the stored data. In addition, the simpler on-chip State-machine design can be achieved with the superior quality of NVMs of this disclosure.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.

Abstract: In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.

Abstract: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

Abstract: A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes first memory blocks configured to store m-bit data per cell and second memory blocks configured to store n-bit data per cell. The memory controller is configured to control the nonvolatile memory device to close an open word line generated in a second memory block of the second memory blocks when a program operation is performed on the second memory block.

Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Abstract: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).

Abstract: A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.