Threshold Setting (e.g., Conditioning) Patents (Class 365/185.24)
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Patent number: 8472245Abstract: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.Type: GrantFiled: January 24, 2011Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Moo Sung Kim
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Patent number: 8472255Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.Type: GrantFiled: September 6, 2012Date of Patent: June 25, 2013Assignee: SanDisk Technologies Inc.Inventors: Nima Mokhlesi, Dengtao Zhao, Henry Chin, Tapan Samaddar
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Patent number: 8472260Abstract: Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a level lower than the first control voltage. The apparatus may also include a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; and a common discharge unit configured to discharge current flowing through the discharge current path.Type: GrantFiled: December 8, 2010Date of Patent: June 25, 2013Assignee: SK Hynix Inc.Inventor: Jae Ho Lee
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Publication number: 20130155776Abstract: A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell.Type: ApplicationFiled: December 13, 2012Publication date: June 20, 2013Applicant: Marvell World Trade Ltd.Inventor: Marvell World Trade Ltd.
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Patent number: 8467249Abstract: A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate a perturbed set of read thresholds. The set of memory cells may be read using the perturbed set of read thresholds to provide a read result. The performance of said reading may be evaluated using the perturbed set of read thresholds. The at least one read threshold may be iteratively perturbed for each sequential read operation that the read performance is evaluated to be sub-optimal.Type: GrantFiled: June 30, 2011Date of Patent: June 18, 2013Assignee: Densbits Technologies Ltd.Inventors: Michael Katz, Hanan Weingarten
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Patent number: 8467248Abstract: Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described.Type: GrantFiled: February 25, 2011Date of Patent: June 18, 2013Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Publication number: 20130148436Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set. The controller reads data from the memory. The controller reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells, calculates difference data on data read at each of the threshold voltages, calculates a minimum value of the distribution of the threshold voltages from the difference data, calculates a range of threshold voltages lower than the minimum value based on the minimum value, and sets a central voltage in the calculated range of threshold voltages as a read voltage.Type: ApplicationFiled: July 9, 2012Publication date: June 13, 2013Inventor: Yasuhiko KUROSAWA
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Patent number: 8462551Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.Type: GrantFiled: December 16, 2011Date of Patent: June 11, 2013Assignee: MOSAID Technologies IncorporatedInventor: Jin-Ki Kim
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Patent number: 8462558Abstract: Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.Type: GrantFiled: August 3, 2010Date of Patent: June 11, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seunghyun Moon, Kihwan Choi, Jaesung Sim, Jungdal Choi
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Patent number: 8462553Abstract: Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.Type: GrantFiled: December 23, 2010Date of Patent: June 11, 2013Assignee: Aplus Flash Technology, Inc.Inventors: Peter Wung Lee, Fu-Chang Hsu
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Patent number: 8462549Abstract: Methods and apparatus are provided for read-side intercell interference mitigation in flash memories. A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.Type: GrantFiled: June 30, 2009Date of Patent: June 11, 2013Assignee: LSI CorporationInventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
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Patent number: 8462559Abstract: Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.Type: GrantFiled: December 20, 2011Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventors: Shigekazu Yamada, Tomoharu Tanaka
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Patent number: 8462548Abstract: A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively.Type: GrantFiled: May 26, 2011Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 8462556Abstract: A localized trapping multi-level memory cell operating method includes the following steps. First, a localized trapping memory cell with the initial threshold voltage of approximately 2.5V is provided. Next, an erasing operation is performed to obtain a negative threshold level having uniform charge distribution along the channel region. Taking into account the over-erasure issue in the erasing operation, a programming operation is performed to precisely adjust the threshold voltage to a predetermined level of ?2V to ?1V. Then, with this negative voltage as a new initial state, a corresponding programming operation is performed and electrons are locally injected into the storage layer. By controlling the quantity of injected electrons, the MLC storage is achieved.Type: GrantFiled: December 15, 2011Date of Patent: June 11, 2013Assignee: Nanjing UniversityInventors: Yue Xu, Feng Yan, Ling Pu, Xiaoli Ji
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Patent number: 8456919Abstract: A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.Type: GrantFiled: November 10, 2011Date of Patent: June 4, 2013Assignee: Sandisk Technologies Inc.Inventors: Seungjune Jeon, Sergey Anatolievich Gorobets
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Patent number: 8456915Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.Type: GrantFiled: March 30, 2012Date of Patent: June 4, 2013Assignee: SanDisk Technologies Inc.Inventors: Changyuan Chen, Jeffrey Lutze, Yingda Dong, Hua-Ling Hsu
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Patent number: 8450121Abstract: A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node.Type: GrantFiled: September 22, 2011Date of Patent: May 28, 2013Assignee: Samsung Display Co., Ltd.Inventor: Kyung-hoon Chung
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Patent number: 8451664Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.Type: GrantFiled: May 12, 2010Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: William H. Radke, Zhenlei Shen, Peter Feeley
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Publication number: 20130128674Abstract: A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.Type: ApplicationFiled: December 4, 2012Publication date: May 23, 2013Applicant: INVENSAS CORPORATIONInventor: INVENSAS CORPORATION
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Patent number: 8446772Abstract: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.Type: GrantFiled: August 4, 2011Date of Patent: May 21, 2013Assignee: SanDisk Technologies Inc.Inventors: Loc Tu, Charles Moana Hook, Nyi Nyi Thein
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Patent number: 8446774Abstract: A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The sense amplifier, during erase verification to determine whether or not a threshold voltage of the memory cell in an erased state is at a threshold level, reads the data from the memory cell and senses the data with a first voltage applied to the control gate of the memory cell, with a positive second voltage higher than the first voltage applied to the semiconductor substrate and the source line, and with a third voltage higher than the second voltage applied to the bit line.Type: GrantFiled: June 6, 2012Date of Patent: May 21, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Maejima
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Patent number: 8446777Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.Type: GrantFiled: October 25, 2011Date of Patent: May 21, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koki Ueno, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa
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Patent number: 8446776Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.Type: GrantFiled: February 8, 2011Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Won Hwang, Chan-Ho Kim
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Publication number: 20130121084Abstract: A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: SEUNGJUNE JEON, SERGEY ANATOLIEVICH GOROBETS
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Patent number: 8441863Abstract: An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.Type: GrantFiled: June 9, 2011Date of Patent: May 14, 2013Assignee: STMicroelectronics S.r.l.Inventors: Maurizio Francesco Perroni, Giuseppe Castagna
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Patent number: 8441858Abstract: Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation.Type: GrantFiled: June 6, 2011Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
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Patent number: 8441056Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.Type: GrantFiled: June 8, 2010Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Leonard Forbes
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Patent number: 8441860Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.Type: GrantFiled: February 6, 2012Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventors: Akira Goda, Taehoon Kim, Doyle Rivers, Roger Porter
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Publication number: 20130114345Abstract: According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.Type: ApplicationFiled: October 18, 2012Publication date: May 9, 2013Inventor: Changhyun LEE
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Patent number: 8437193Abstract: An apparatus and method for selectively controlling application of a data recovery bias voltage are described. One example apparatus includes replenish logic configured to selectively control application of a data recovery bias voltage to a control gate associated with a cell in a flash memory apparatus. The replenish logic may be configured to select the data recovery bias voltage to replenish charge lost from a floating gate in the flash memory apparatus. The replenish logic may also be configured to control application of the data recovery bias voltage for a period of time sufficient to charge a threshold voltage (Vt) in the cell. In one embodiment, the data recovery bias voltage is based on a program voltage employed to program a value into the cell.Type: GrantFiled: June 22, 2010Date of Patent: May 7, 2013Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8437186Abstract: Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.Type: GrantFiled: June 12, 2012Date of Patent: May 7, 2013Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 8432733Abstract: Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming.Type: GrantFiled: April 11, 2011Date of Patent: April 30, 2013Assignee: SanDisk Technologies Inc.Inventor: Masaaki Higashitani
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Patent number: 8432741Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.Type: GrantFiled: March 14, 2012Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jae Lee, Dae-Seok Byeon, Hyun-Chul Ha
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Patent number: 8432743Abstract: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed.Type: GrantFiled: December 9, 2011Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventor: Amin Khaef
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Patent number: 8427877Abstract: A calibration table (160) of reference current (Iref) values and associated digital register settings is used during user test/diagnostics mode by varying the Iref values by changing the digital register settings and searching the transitioning gate voltage (Vg) of each bitcell at each Iref value to obtain the bitcell I-V curve using a digitally tunable gate voltage control (117) and reference current circuit (123) under control of a test module or circuit (110).Type: GrantFiled: February 11, 2011Date of Patent: April 23, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Chen He, Richard K. Eguchi
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Patent number: 8427880Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states.Type: GrantFiled: July 23, 2010Date of Patent: April 23, 2013Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 8427879Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.Type: GrantFiled: December 22, 2009Date of Patent: April 23, 2013Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
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Patent number: 8427870Abstract: Provided is a method for operating a nonvolatile memory device. In the method, read data is read by means of a read level and logic values for erasure-decoding the read data are set. The bits of the read data corresponding to the range of the set logic values is set as erasure bits, and an erasure decoding operation is performed.Type: GrantFiled: February 16, 2010Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong June Kim, Jaehong Kim, Heeseok Eun
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Publication number: 20130094294Abstract: Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of verification voltages having different levels according to a result of the state read operation. Also disclosed are methods using a plurality of verification voltages selected based on factors which may affect a threshold voltage shift or other characteristic representing the data of a memory cell after programming.Type: ApplicationFiled: October 10, 2012Publication date: April 18, 2013Inventors: DongHun KWAK, Sang-Won PARK, Won-Taeck JUNG
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Patent number: 8422311Abstract: A EPROM erasing apparatus and method for erasing an EPROM(s). The EPROM(s) is erased using light emitted from an ultraviolet light emitting diode.Type: GrantFiled: July 30, 2010Date of Patent: April 16, 2013Assignee: The United States of America as Represented by the Secretary of the NavyInventors: Marion Joseph Roberts, Timothy Mark Ochoa
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Patent number: 8422303Abstract: A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write VT and variable read VT. Techniques for early degradation detection (EDD) in Flash memories measure the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values.Type: GrantFiled: December 22, 2010Date of Patent: April 16, 2013Assignee: HGST Netherlands B.V.Inventors: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
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Patent number: 8422301Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.Type: GrantFiled: June 27, 2011Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Eietsu Takahashi, Yuji Takeuchi
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Patent number: 8422307Abstract: A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.Type: GrantFiled: June 10, 2010Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Han Woong Yoo, Seung-Hwan Song, Hee seok Eun, Jun jin Kong
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Patent number: 8422292Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.Type: GrantFiled: May 3, 2011Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Hee Choi, BoGeun Kim
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Patent number: 8422304Abstract: A method of manufacturing a flash memory device is provided. First and second gates are formed on first and second dielectrics and spaced apart from each other on a cell area of a substrate. A third gate is formed on a third dielectric that is formed on first opposing sidewalls of the first gate and extending on a portion of the substrate from the first opposing sidewalls. A fourth gate is formed on a fourth dielectric that is formed on second opposing sidewalls of the second gate and extending on a portion of the substrate from the second opposing sidewalls. The third gate and third dielectric on one of the first opposing sidewalls facing the second gate and the fourth gate and fourth dielectric on one of the second opposing sidewalls facing the first gate are removed. Drain areas are formed at outer sides of the third and fourth gates, and a common source area is formed between the first and second gates.Type: GrantFiled: December 16, 2010Date of Patent: April 16, 2013Assignee: Dongbu Hitek Co., Ltd.Inventor: Dae Il Kim
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Publication number: 20130088923Abstract: A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data.Type: ApplicationFiled: November 29, 2012Publication date: April 11, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SAMSUNG ELECTRONICS CO., LTD.
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Patent number: 8416626Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.Type: GrantFiled: September 20, 2011Date of Patent: April 9, 2013Assignee: SanDisk Technologies Inc.Inventor: Gerrit Jan Hemink
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Publication number: 20130083608Abstract: The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value.Type: ApplicationFiled: September 29, 2011Publication date: April 4, 2013Applicant: Cypress Semiconductor CorporationInventors: Venkatraman Prabhakar, Frederick Jenne
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Patent number: 8411503Abstract: A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.Type: GrantFiled: December 30, 2010Date of Patent: April 2, 2013Assignee: Hynix Semiconductor Inc.Inventor: Min Kyu Lee
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Patent number: 8411510Abstract: A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed.Type: GrantFiled: March 4, 2011Date of Patent: April 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Rak Son, Han-Woong Yoo, Jun-Jin Kong, Hee-Seok Eun