Floating Electrode (e.g., Source, Control Gate, Drain) Patents (Class 365/185.26)
  • Patent number: 10971232
    Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-bo Shim, Ji-ho Cho, Yong-seok Kim, Byoung-taek Kim, Sun-gyung Hwang
  • Patent number: 10797069
    Abstract: A semiconductor memory device includes a semiconductor substrate, a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate, a plurality of first memory cells arranged on a first side surface of the pillar along the first direction, and a plurality of second memory cells arranged on a second side surface of the pillar along the first direction. The memory device further includes a plurality of first control gate layers respectively connected to the first memory cells, a plurality of second control gate layers respectively connected to the second memory cells, and a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaki Kondo
  • Patent number: 10771091
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 8, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10083747
    Abstract: A reconfigurable phase change device with methods for operating and forming the same are disclosed. An example device can comprise a reconfigurable layer comprising a phase change material, and a set of contacts connected with the reconfigurable layer. The set of contacts can comprise at least a first contact, a second contact, and a third contact. The device can comprise at least one control element electrically coupled with one or more of the set of contacts. The at least one control element can be configured to supply a first control signal to one or more of the set of contacts. The first control signal can be configured to modify a first portion of the reconfigurable layer thereby isolating the first contact from the second contact and the third contact.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 25, 2018
    Assignee: UNIVERSITY OF CONNECTICUT
    Inventors: Nadim H. Kan'an, Ali Gokirmak, Helena Silva
  • Patent number: 9985126
    Abstract: A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventor: Andreas Meiser
  • Patent number: 9922987
    Abstract: Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuki Mizutani, James Kai, Fumiaki Toyama, Shigehiro Fujino, Johann Alsmeier
  • Patent number: 9373407
    Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 21, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Yao Zhou, Xiaozhou Qian, Ning Bai
  • Patent number: 9240242
    Abstract: A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 19, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Yang-Sen Yeh, Cheng-Ying Wu
  • Patent number: 9218882
    Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Fukuda
  • Patent number: 9025373
    Abstract: According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Koichiro Zaitsu, Mari Matsumoto, Shinichi Yasuda
  • Patent number: 9019769
    Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee
  • Patent number: 9007842
    Abstract: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Jeremy Werner, Ying Quan Wu, Erich F. Haratsch
  • Patent number: 8988939
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Patent number: 8988937
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Patent number: 8982641
    Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 17, 2015
    Assignee: EON Silicon Solution Inc.
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Yu-Chun Wang
  • Patent number: 8953371
    Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi, Koki Ueno
  • Patent number: 8942053
    Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ji Lu, Hung-Jen Liao, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng
  • Patent number: 8942035
    Abstract: Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Patrick J. Ryan
  • Patent number: 8934299
    Abstract: To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor. With the structure, a desired potential can be stored as data without an increase in the number of power source potentials.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda
  • Patent number: 8923059
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 30, 2014
    Assignee: SK hynix Inc.
    Inventor: Han Soo Joo
  • Publication number: 20140369135
    Abstract: An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating with no voltage bias to prevent applied electrical fields toward the source electrode. The drain electrode of the N-channel semiconductor NVM is reversely biased with a positive voltage VDB relative to the substrate to facilitate the valence band electrons in the P-type substrate to tunnel to the conducting band of the N-type drain electrode. A positive high gate voltage pulse is then applied to the gate electrode of the N-channel semiconductor NVM to collect the surface energetic electrons toward the charge storage material.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventor: Lee WANG
  • Patent number: 8908435
    Abstract: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 9, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Haibo Li, Xiying Costa, Chenfeng Zhang
  • Patent number: 8907396
    Abstract: Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc
    Inventors: John Hopkins, James Mathew, Jie Sun, Gordon Haller
  • Patent number: 8902640
    Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Takanori Matsuzaki, Shuhei Nagatsuka
  • Patent number: 8902658
    Abstract: Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: December 2, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Raghu, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui, Pao-Ling Koh
  • Patent number: 8891315
    Abstract: A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: ChangHyun Lee, Byoungkeun Son
  • Patent number: 8891310
    Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 8885420
    Abstract: Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to 0V). However, the voltage applied to an edge word may be increased in magnitude relative to a previous voltage applied to the edge word line for at least a portion of the sequence of erase voltages. The edge word line could be the word line that is immediately adjacent to the select line. The increasing voltage applied to the edge word line may prevent or reduce damage to oxides between the select line and edge word line. It may also help to regulate the e-field across a tunnel oxide of memory cells on the edge word line.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: November 11, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Ken Oowada, Deepanshu Dutta
  • Patent number: 8885412
    Abstract: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 11, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Haibo Li, Xiying Costa, Chenfeng Zhang
  • Patent number: 8885416
    Abstract: Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Man L. Mui, Teruhiko Kamei, Yingda Dong, Ken Oowada, Yosuke Kato, Fumitoshi Ito, Seungpil Lee
  • Patent number: 8879323
    Abstract: An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 4, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8861281
    Abstract: A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: October 14, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ping-Hung Tsai, Jyun-Siang Huang, Wen-Jer Tsai
  • Patent number: 8848452
    Abstract: Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: September 30, 2014
    Assignee: Spansion LLC
    Inventor: Sameer Haddad
  • Patent number: 8848453
    Abstract: An apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke
  • Patent number: 8837219
    Abstract: Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Kai-Yuan Hsiao, Wen-Yuan Lee, Yun-Jen Ting, Cheng-Jye Liu, Wein-Town Sun
  • Patent number: 8837227
    Abstract: A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 16, 2014
    Assignee: National Tsing Hua University
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Patent number: 8837221
    Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations. The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: September 16, 2014
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Fu-Chang Hsu
  • Patent number: 8837202
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1—n—m and STr2—n—m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2—n—m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8824210
    Abstract: The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 2, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Patent number: 8817546
    Abstract: Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: August 26, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8809931
    Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Nobutoshi Aoki, Takashi Izumida, Masaki Kondo, Toshiyuki Enda
  • Publication number: 20140226416
    Abstract: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Haibo Li, Xiying Costa, Chenfeng Zhang
  • Patent number: 8804430
    Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 12, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Chun-Hung Lai, Shinji Sato, Shih-Chung Lee, Gerrit Jan Hemink
  • Patent number: 8803214
    Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 8797806
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 8792276
    Abstract: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Serguei Okhonin
  • Patent number: 8787082
    Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Youngsoo An, Mingu Kim, Jinho Kim, Jaehyoung Choi, Sukhun Choi, Jae-Joo Shim, Wonseok Cho, Sunil Shim, Ju-Young Lim
  • Patent number: 8780625
    Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 15, 2014
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jing Gu, Bo Zhang, Weiran Kong, Jian Hu
  • Patent number: 8772853
    Abstract: A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: July 8, 2014
    Assignee: The Regents of the University of California
    Inventors: Augustin J. Hong, Ji-Young Kim, Kang-Lung Wang
  • Patent number: 8760934
    Abstract: A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Sang Hyun Oh