Floating Electrode (e.g., Source, Control Gate, Drain) Patents (Class 365/185.26)
  • Patent number: 11972114
    Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sandeep Reddy Kadasani, Pitamber Shukla, Scott Anthony Stoller, Niccolo' Righetti
  • Patent number: 11961472
    Abstract: A pixel driving circuit, a display panel, and an electronic device. The pixel driving circuit includes: a pixel array including a plurality of pixel circuits, an RGBG pixel arrangement mode being adopted in the pixel array; at least four gate lines, arranged in a first direction of the pixel array, one row of pixel circuits being arranged between every two adjacent gate lines, and each row of pixel circuits corresponding to one gate line; at least eight data lines, arranged in a second direction perpendicular to the first direction and intersecting each gate line, each data line being connected to pixel circuits corresponding to sub-pixels of the same color in one column of pixel circuits; and a demultiplexer circuit, connected to the data lines, and configured to control the data lines to be in communication with an integrated circuit chip.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: April 16, 2024
    Assignee: Vivo Mobile Communication Co., Ltd.
    Inventor: Caiqin Chen
  • Patent number: 11941324
    Abstract: A method of manufacturing an interface for a body part using an additive manufacturing process is described. The method obtaining a digital model of the body part and modifying the digital model to create a plurality of compression areas. The compression areas are spaced circumferentially around a long axis of the digital model to create a compression pattern. The compression pattern is sized and dimensioned to compress soft tissue of the body part against the skeletal structure such that motion of the skeletal structure towards a wall of the interface is reduced.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: March 26, 2024
    Inventors: Randall D. Alley, T. Walley Williams, III
  • Patent number: 11903207
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 11894059
    Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Dong Hun Kwak
  • Patent number: 11894038
    Abstract: Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Daeshik Kim
  • Patent number: 11886718
    Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
  • Patent number: 11847990
    Abstract: A display device can include a left ripple transistor provided in a left stage to remove ripple occurring in a Q node of the left stage, and a right ripple transistor provided in a right stage to remove ripple occurring in a Q node of the right stage. These ripple transistors perform an on operation and an off operation repeatedly and simultaneously.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: December 19, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: MyungHo Ban, Hyunsuk Lee
  • Patent number: 11817453
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Patent number: 11810621
    Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Robert W. Strong, William Akin, Jeremy Binfet
  • Patent number: 11783902
    Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Nevil N. Gajera
  • Patent number: 11769552
    Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11735280
    Abstract: A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gu-Huan Li, Tung-Cheng Chang, Perng-Fei Yuh, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Patent number: 11735255
    Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Corrado Villa, Ferdinando Bedeschi, Paolo Fantini
  • Patent number: 11716852
    Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventor: Takeshi Kamigaichi
  • Patent number: 11710525
    Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • Patent number: 11695082
    Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 11688469
    Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: June 27, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Gerrit Jan Hemink, Xiang Yang, Ken Oowada, Guirong Liang
  • Patent number: 11626175
    Abstract: Various embodiments of the present disclosure generally relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check first information indicating an execution state of a reference operation on each of the memory blocks during a preset target time period, may determine, based on the first information, at least one target memory block, among the plurality of memory blocks, as a target of a refresh operation of rewriting data stored in the target memory block and may execute a refresh operation on the target memory block.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 11, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyeong Ju Na
  • Patent number: 11621335
    Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 4, 2023
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
  • Patent number: 11610906
    Abstract: First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 21, 2023
    Assignee: Tower Partners Semiconductor Co., Ltd.
    Inventors: Hiroshige Hirano, Hiroaki Kuriyama
  • Patent number: 11574681
    Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 7, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Takashi Ishida, Hiroshi Kanno
  • Patent number: 11551761
    Abstract: In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 10, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Deepanshu Dutta
  • Patent number: 11521687
    Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: December 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuharu Yamabe, Qianqian Xu
  • Patent number: 11450386
    Abstract: A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.
    Type: Grant
    Filed: April 4, 2021
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmin Joe, Sangsoo Park, Joonsuc Jang, Kihoon Kang, Yonghyuk Choi
  • Patent number: 11450677
    Abstract: A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 20, 2022
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Xinshu Cai, Eng Huat Toh, Yongshun Sun
  • Patent number: 11430521
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 30, 2022
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11380692
    Abstract: A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • Patent number: 11309037
    Abstract: A voltage switching circuit selectively transfers voltages applied to a first input terminal and a second input terminal to a first output terminal and a second output terminal. The voltage switching circuit includes a first transistor and a second transistor. The first transistor is formed on a first well on a substrate, and is coupled between the first input terminal and the first output terminal. The second transistor is formed on a second well different from the first well, and is coupled to the second input terminal. In a first mode in which a first voltage applied to the first input terminal is transferred to the first output terminal and the second output terminal, the first transistor is turned on and the second transistor is turned off.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Wan Chae
  • Patent number: 11264108
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 11205488
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 11018153
    Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 25, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Murshed Chowdhury
  • Patent number: 10971232
    Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-bo Shim, Ji-ho Cho, Yong-seok Kim, Byoung-taek Kim, Sun-gyung Hwang
  • Patent number: 10797069
    Abstract: A semiconductor memory device includes a semiconductor substrate, a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate, a plurality of first memory cells arranged on a first side surface of the pillar along the first direction, and a plurality of second memory cells arranged on a second side surface of the pillar along the first direction. The memory device further includes a plurality of first control gate layers respectively connected to the first memory cells, a plurality of second control gate layers respectively connected to the second memory cells, and a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaki Kondo
  • Patent number: 10771091
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 8, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10083747
    Abstract: A reconfigurable phase change device with methods for operating and forming the same are disclosed. An example device can comprise a reconfigurable layer comprising a phase change material, and a set of contacts connected with the reconfigurable layer. The set of contacts can comprise at least a first contact, a second contact, and a third contact. The device can comprise at least one control element electrically coupled with one or more of the set of contacts. The at least one control element can be configured to supply a first control signal to one or more of the set of contacts. The first control signal can be configured to modify a first portion of the reconfigurable layer thereby isolating the first contact from the second contact and the third contact.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 25, 2018
    Assignee: UNIVERSITY OF CONNECTICUT
    Inventors: Nadim H. Kan'an, Ali Gokirmak, Helena Silva
  • Patent number: 9985126
    Abstract: A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventor: Andreas Meiser
  • Patent number: 9922987
    Abstract: Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuki Mizutani, James Kai, Fumiaki Toyama, Shigehiro Fujino, Johann Alsmeier
  • Patent number: 9373407
    Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 21, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Yao Zhou, Xiaozhou Qian, Ning Bai
  • Patent number: 9240242
    Abstract: A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 19, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Yang-Sen Yeh, Cheng-Ying Wu
  • Patent number: 9218882
    Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Fukuda
  • Patent number: 9025373
    Abstract: According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Koichiro Zaitsu, Mari Matsumoto, Shinichi Yasuda
  • Patent number: 9019769
    Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee
  • Patent number: 9007842
    Abstract: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Jeremy Werner, Ying Quan Wu, Erich F. Haratsch
  • Patent number: 8988937
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Patent number: 8988939
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Patent number: 8982641
    Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 17, 2015
    Assignee: EON Silicon Solution Inc.
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Yu-Chun Wang
  • Patent number: 8953371
    Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Shiino, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi, Koki Ueno
  • Patent number: 8942053
    Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ji Lu, Hung-Jen Liao, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng
  • Patent number: 8942035
    Abstract: Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Patrick J. Ryan