Floating Electrode (e.g., Source, Control Gate, Drain) Patents (Class 365/185.26)
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Publication number: 20120287724Abstract: A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ping-Hung Tsai, Jyun-Siang Huang, Wen-Jer Tsai
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Patent number: 8305790Abstract: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.Type: GrantFiled: March 16, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tao-Wen Chung, Po-Yao Ke, Shine Chung, Fu-Lung Hsueh
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Patent number: 8295087Abstract: A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells.Type: GrantFiled: June 16, 2009Date of Patent: October 23, 2012Assignee: Aplus Flash Technology, Inc.Inventors: Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao
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Patent number: 8295090Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.Type: GrantFiled: June 17, 2010Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
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Patent number: 8294193Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation.Type: GrantFiled: October 29, 2010Date of Patent: October 23, 2012Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 8284616Abstract: Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.Type: GrantFiled: November 22, 2010Date of Patent: October 9, 2012Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Patent number: 8284601Abstract: A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.Type: GrantFiled: April 1, 2010Date of Patent: October 9, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Byoungkeun Son, Hansoo Kim, Youngsoo An, Mingu Kim, Jinho Kim, Jaehyoung Choi, Sukhun Choi, Jae-Joo Shim, Wonseok Cho, Sunil Shim, Ju-Young Lim
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Patent number: 8284600Abstract: A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.Type: GrantFiled: February 8, 2010Date of Patent: October 9, 2012Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Ernes Ho, Umer Khan, Hengyang James Lin
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Patent number: 8270213Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: December 7, 2010Date of Patent: September 18, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 8264889Abstract: A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory device by applying a first voltage to the pair of conductive layers and heating the organic compound, to cause a phase change of the organic compound from a first phase to a second phase.Type: GrantFiled: December 30, 2009Date of Patent: September 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Nobuharu Ohsawa
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Patent number: 8264030Abstract: A flash memory device and a method for manufacturing the same are provided. The flash memory device can include first and second memory gates on a substrate, an oxide layer on sides of and on the substrate outside of the first and second memory gates, a source poly contact between the first and second memory gates, first and second select gates outside the first and second memory gates, a drain region outside the first and second select gates, and a metal contact on the drain region and the source poly contact.Type: GrantFiled: December 21, 2009Date of Patent: September 11, 2012Assignee: Dongbu Hitek Co., Ltd.Inventor: Young Jun Kwon
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Patent number: 8253185Abstract: A memory device includes gate lines and select lines formed over a substrate, and at least two dummy lines formed in a gap region between adjacent select lines. The memory device is able to reduce a width of the select line by enhancing uniformity of the line pattern density. Therefore, a degree of integration of the memory device is enhanced and the cost of production is reduced. Furthermore, by forming a source line in a gap region between adjacent dummy lines, it is possible to secure a process margin of photolithography for forming a contact hole and to reduce contact resistance.Type: GrantFiled: March 27, 2009Date of Patent: August 28, 2012Assignee: Hynix Semiconductor Inc.Inventor: Nam-Jae Lee
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Publication number: 20120206979Abstract: A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures.Type: ApplicationFiled: February 15, 2012Publication date: August 16, 2012Inventors: Hack Seob Shin, Sang Hyun Oh
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Publication number: 20120201084Abstract: A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating.Type: ApplicationFiled: February 4, 2011Publication date: August 9, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yvonne LIN, Tien-Chun YANG
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Patent number: 8237218Abstract: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.Type: GrantFiled: September 6, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Murata, Takeshi Kamigaichi
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Patent number: 8238144Abstract: A spin-transfer magnetic memory includes a magnetoresistive element having a pinned layer, a free layer and a tunnel insulating layer provided between the pinned layer and the free layer, a bit line connected to one terminal of the magnetoresistive element, a select transistor having a current path whose one terminal is connected to the other terminal of the magnetoresistive element, a source line connected to the other terminal of the current path of the select transistor, and a pulse generation circuit passing a microwave pulse current through the magnetoresistive element, and assisting a magnetization switching of the free layer in a write operation.Type: GrantFiled: March 3, 2010Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8238170Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.Type: GrantFiled: March 10, 2010Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, William Kueber, Mark Helm
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Patent number: 8228708Abstract: In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2<Vs, and V2<Vd, are applied to write a second resistance value, and (3) the voltages V1, V2, Vs, and Vd, which satisfy V1<Vs, V1<Vd, V2<Vs, and V2<Vd, are applied to write a third resistance value.Type: GrantFiled: August 31, 2011Date of Patent: July 24, 2012Assignee: Panasonic CorporationInventors: Yukihiro Kaneko, Hiroyuki Tanaka, Michihito Ueda
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Patent number: 8223571Abstract: A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.Type: GrantFiled: July 20, 2010Date of Patent: July 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ji Lu, Hung-Jen Liao, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng
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Patent number: 8223553Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.Type: GrantFiled: October 12, 2005Date of Patent: July 17, 2012Assignee: Macronix International Co., Ltd.Inventors: Chih Chieh Yeh, Wen Jer Tsai, Yi Ying Liao
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Patent number: 8218364Abstract: An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N?1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.Type: GrantFiled: June 13, 2011Date of Patent: July 10, 2012Assignee: Macronix International Co., Ltd.Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
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Patent number: 8213225Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.Type: GrantFiled: March 28, 2011Date of Patent: July 3, 2012Assignee: Micron Technology, Inc.Inventor: Sanh D. Tang
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Patent number: 8213238Abstract: A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation.Type: GrantFiled: December 21, 2009Date of Patent: July 3, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Jin-Hyo Jung
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Patent number: 8199560Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.Type: GrantFiled: June 9, 2011Date of Patent: June 12, 2012Assignee: Infineon Technologies AGInventors: Ronald Kakoschke, Harald Seidl
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Patent number: 8194467Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.Type: GrantFiled: March 17, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshimasa Mikajiri, Ryouhei Kirisawa, Masaru Kito, Shigeto Oota
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Patent number: 8194468Abstract: A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.Type: GrantFiled: June 10, 2011Date of Patent: June 5, 2012Assignee: Synopsys, Inc.Inventor: Andrew E. Horch
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Patent number: 8189377Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: GrantFiled: February 24, 2011Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Kazuyoshi Shiba, Yasushi Oka
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Patent number: 8184482Abstract: A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral element and configured to generate a negative voltage.Type: GrantFiled: December 29, 2009Date of Patent: May 22, 2012Assignee: Hynix Semiconductor Inc.Inventor: Cheul Hee Koo
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Patent number: 8179724Abstract: Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.Type: GrantFiled: February 18, 2011Date of Patent: May 15, 2012Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
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Publication number: 20120113713Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: Micron Technology, Ind.Inventor: Akira Goda
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Patent number: 8174885Abstract: The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.Type: GrantFiled: May 2, 2011Date of Patent: May 8, 2012Assignee: Halo LSI Inc.Inventors: Tomoko Ogura, Nori Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba
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Patent number: 8169828Abstract: A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line.Type: GrantFiled: December 17, 2009Date of Patent: May 1, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Jin-Hyo Jung
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Patent number: 8159861Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: April 20, 2010Date of Patent: April 17, 2012Assignee: Broadcom CorporationInventor: Sami Issa
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Patent number: 8159878Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation.Type: GrantFiled: October 29, 2010Date of Patent: April 17, 2012Assignee: ZENO Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 8154930Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.Type: GrantFiled: May 7, 2010Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Shibata, Tomoharu Tanaka
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Patent number: 8149622Abstract: A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.Type: GrantFiled: February 5, 2010Date of Patent: April 3, 2012Assignee: Aplus Flash Technology, Inc.Inventors: Peter Wung Lee, Fu-Chang Hsu, Kesheng Wang
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Patent number: 8139416Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.Type: GrantFiled: June 13, 2011Date of Patent: March 20, 2012Assignee: Macronix International Co., Ltd.Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
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Patent number: 8130955Abstract: Systems and/or methods that facilitate security of data are presented. A random number generation component generates random numbers based in part on electron activity in a select memory cell(s) to facilitate data security. Sensor components that are highly sensitive can be employed to sense activity of the select memory cell(s) and/or reference memory cell in a noise margin associated with respective memory cells in the memory component. The activity of the select memory cell is compared to the reference memory cell(s) to facilitate generating binary data. The binary data is provided to the random number generation component where the binary data is evaluated to determine whether a predetermined level of entropy exists in the binary data. The binary data, or a portion thereof, can be processed to generate random numbers that are utilized in cryptographic processes and/or as a physical signature to facilitate data security.Type: GrantFiled: December 21, 2007Date of Patent: March 6, 2012Assignee: Spansion LLCInventors: Elena Trichina, Helena Handschuh
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Patent number: 8125831Abstract: Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.Type: GrantFiled: November 29, 2010Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Vishal Sarin
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Patent number: 8107290Abstract: A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.Type: GrantFiled: April 1, 2008Date of Patent: January 31, 2012Assignee: The Regents of the University of MichiganInventors: Yoonmyung Lee, Michael John Wieckowski, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Patent number: 8107300Abstract: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.Type: GrantFiled: February 4, 2008Date of Patent: January 31, 2012Assignee: Genusion, Inc.Inventors: Taku Ogura, Natsuo Ajika
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Patent number: 8102714Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.Type: GrantFiled: February 3, 2010Date of Patent: January 24, 2012Assignee: Round Rock Research, LLCInventors: Chun Chen, Kirk D. Prall
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Patent number: 8098529Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.Type: GrantFiled: March 11, 2009Date of Patent: January 17, 2012Assignee: Micron Technology, Inc.Inventor: Akira Goda
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Patent number: 8094497Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.Type: GrantFiled: March 9, 2010Date of Patent: January 10, 2012Assignee: Macronix International Co., Ltd.Inventors: Hang-Ting Lue, Szu-Yu Wang
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Patent number: 8089815Abstract: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.Type: GrantFiled: November 24, 2009Date of Patent: January 3, 2012Assignee: SanDisk Technologies Inc.Inventors: Yan Li, Anubhav Khandelwal
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Patent number: 8081509Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.Type: GrantFiled: April 23, 2010Date of Patent: December 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Yong Kim, Sang-Won Hwang, Jun-Yong Park
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Patent number: 8077523Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.Type: GrantFiled: March 18, 2009Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nakano, Hiroshi Nakamura, Koji Hosono
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Patent number: 8077519Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.Type: GrantFiled: December 30, 2010Date of Patent: December 13, 2011Assignee: Micron Technology, Inc.Inventor: Frankie F. Roohparvar
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Publication number: 20110280085Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: ApplicationFiled: July 28, 2011Publication date: November 17, 2011Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Patent number: 8059446Abstract: An integrated circuit with memory having a current limiting switch includes a memory cell having a programmable resistivity layer and a writing line. A switch is arranged between the resistivity layer and the writing line. The switch includes a control input connected to a select line. The switch is configured to limit a current through the resistivity layer for a write operation.Type: GrantFiled: September 8, 2008Date of Patent: November 15, 2011Assignee: Qimonda AGInventor: Ralf Symanczyk