Abstract: A load modulation device in a remotely powered integrated circuit includes an oscillating circuit, and a voltage device for regenerating first and second power supply voltages. The voltage device includes at least one MOS transistor in a well on at least one terminal of the oscillating circuit. The at least MOS transistor includes a source or drain connected to the at least one terminal. A bias circuit biases the well to the first or second power supply voltage based upon a modulation signal.

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

Abstract: Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of erasing the memory cell by withdrawing negative charge from a floating gate therein using a positive control electrode bias and a negative substrate bias. The use of a negative substrate bias increases the potential difference between the control electrode and the floating gate and this increase results in faster and more reliable erasing. A step is also performed to program the memory cell by accumulating negative charge on the floating gate using a positive control electrode bias, a negative substrate bias and a positive drain bias. Here, the negative substrate bias is used advantageously to reduce the likelihood that non-selected memory cells will become inadvertently programmed during operations to program selected memory cells.

Abstract: A method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell, wherein the source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.

Abstract: A method for reading flash memory cell with SONOS structure is disclosed. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trapping layer, a gate conductive layer on the dielectric layer, and source and drain regions in the substrate adjacent to the gate conductive layer. The flash memory cell with SONOS structure is read by applying a positive voltage to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: In a semiconductor memory device the potential of a semiconductor substrate and that of all of a plurality of word lines are increased to an erase voltage by means of a boosting circuit, and subsequently the potential of the word line selected by a word line selection circuit is decreased, when data of a memory cell is erased.

Abstract: A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area.

Abstract: The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavy doping. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current require for Channel Hot Electron Injection (CHEI) programming. Furthermore, before erasing the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.

Abstract: According to the present invention, a voltage of 10.5 V, a voltage of 6.5 V and a voltage of 0.5 V are respectively applied to the control gate, the drain and the source of a memory cell that is a programming target. And a voltage of 0 V (a ground voltage) is applied to the control gate of a memory cell that is not a programming target and that does not belong to the row in which of the programming target memory cell is located. As a result, it is ensured that the memory cell that is not the programming target is non-conductive, and that the drain-substrate electrical field of the memory cell that is the programming target is reduced.

Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: A nonvolatile semiconductor memory device having a memory cell comprising source/drain diffusion layer in p-well formed to a silicon substrate, a floating gate as a first gate, a control gate (word line) as a second gate, and a third gate, in which the floating gate and the p-well are isolated by a tunnel insulator film, the third gate and the p-well are isolated by a gate insulator film, the floating gate and the third gate are isolated by an insulator film, the floating gate and the word line (control gate) are isolated by a insulator film (ONO film), and the second gate film and the word line (control gate) are isolated by a silicon oxide film, respectively, wherein the thickness of the tunnel insulator film is made larger than the thickness of the gate insulator film. Accordingly, the reliability and access time of the device is improved.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a VPP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: A semiconductor device capable of achieving a cost reduction by increasing the common steps in the production of different kinds of transistors in addition to reducing the area of the memory peripheral circuit, comprising a first voltage supplying circuit, as a write and erase circuit for supplying a write voltage or an erase voltage to non-volatile memory transistors, dividing the write voltage to a first and a second voltage and supplying the first voltage to a gate electrode (word line) at the time of a write operation and for dividing the erase voltage to a third and fourth voltage and supplying the third voltage at an opposite polarity from the first voltage to the word line at the time of an erase operation, and a second voltage supply circuit for applying the second voltage at an opposite polarity from the time of applying the first voltage to the semiconductor substrate or well at the time of a write operation and for applying the fourth voltage at an opposite polarity from the time of applying the th

Abstract: A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

Abstract: A charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; and power supply generation circuit, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation circuit is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.

Abstract: A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment, a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Abstract: A load modulation device in a remotely powered integrated circuit includes an oscillating circuit, and a voltage device for regenerating first and second power supply voltages. The voltage device includes at least one MOS transistor in a well on at least one terminal of the oscillating circuit. The at least MOS transistor includes a source or drain connected to the at least one terminal. A bias circuit biases the well to the first or second power supply voltage based upon a modulation signal.

Abstract: A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.

Abstract: Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design.

Abstract: A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of −5˜−7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes electrons to be injected from a source 116 and a drain 117 into the channel (P-type well 123) (a). As the voltage applied to the P-type well 123 changes to −5 V, a depletion layer 124 is formed at the channel. At the depletion layer 124, the electrons are accelerated toward a tunnel oxide film 111 (b). The electrons having been accelerated in the channel are injected into the tunnel oxide film 111, are allowed to move inside the tunnel oxide film 111 by the electrical field at the tunnel oxide film 111 and are finally trapped at a floating gate 113.

Abstract: A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.

Abstract: The cells of a memory cell array are programmed in a pair wise manner. The pairs are separated by at least one memory cell, reducing the possibility of interference between the pairs during programming. The memory cells are programmed individually by applying a relatively high voltage to one of the bit lines of each cell regardless whether the cells are to be programmed or not, while applying a lower voltage to the second bit lines, depending on whether the cells are to be programmed or not. This programming voltage assignment enhances the speed of programming. Furthermore, the pair wise programming scheme applies the necessary high voltages only half as often as in previous schemes to program all the cells of the array, increasing the lifetime of the memory system.

Abstract: A method of erasing a memory cell with a substrate that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across said the region. A third constant voltage is applied in a region of the substrate outside of the first and second regions so that a first portion of the first amount of charge is removed from the charge trapping region.

Abstract: A method for programming a NAND-type flash memory device is provided. In the method for programming a NAND-type flash memory device having a plurality of strings two dimensionally arranged on the bulk area of a first conductivity type and a plurality of bitlines arranged in parallel on the plurality of strings, a bulk bias corresponding to a reverse bias is applied to the bulk area of the first conductivity type. At least one bitline is selected among the plurality of bitlines. At least one string is selected from among the plurality of strings connected to the selected bitline in parallel. At least one cell is programmed from among the plurality of cells within the selected strings.

Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Abstract: A non-volatile memory device including a cell array region formed having a plurality of parallel bit lines, a plurality of parallel word lines, a plurality of memory cells, and a plurality of common source lines, the plurality of bit lines being orthogonal to the plurality of word lines, each of the memory cells being connected to a bit line and a word line and having a stacked gate comprised of a floating gate and a control gate and a source/drain region, the plurality of common source lines being parallel to the plurality of bit lines. The non-volatile memory device also includes a peripheral circuit region for driving the memory cells in the cell array region is formed. The cell array region includes one or more bulk bias contact structures for maintaining the voltage of a bulk region in which the cell array region is formed, at or below a predetermined voltage.

Abstract: Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of erasing the memory cell by withdrawing negative charge from a floating gate therein using a positive control electrode bias and a negative substrate bias. The use of a negative substrate bias increases the potential difference between the control electrode and the floating gate and this increase results in faster and more reliable erasing. A step is also performed to program the memory cell by accumulating negative charge on the floating gate using a positive control electrode bias, a negative substrate bias and a positive drain bias. Here, the negative substrate bias is used advantageously to reduce the likelihood that non-selected memory cells will become inadvertently programmed during operations to program selected memory cells.

Abstract: A stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized to form a first dielectric layer over the sidewalls of the control-gate layer, a second dielectric layer over the sidewalls of the floating-gate layer, and a thicker oxide layer over each side portion of the active region having a gradedoxide layer formed near two gate edges. An integrated source/drain landing island having a portion formed over a source/drain diffusion region for contact and an extended portion formed over a second dielectric layer and on a graded-oxide layer is acted as a field-emission cathode/anode. The scaled stack-gate flash memory device of the present invention can be programmed and erased through two-tunneling paths or one tunneling path without involving the channel region.

Abstract: A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and array architecture. The floating-gate memory cells may be programmed using band-to-band tunneling. The floating-gate memory cells may be read using capacitance sensing or forward current sensing techniques.

Abstract: A memory cell that includes a substrate that has a first region and a second region with a channel therebetween. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge, wherein the first region is doped to such an extent that electric fields are reduced at the locations in the substrate where impact ionization occurs during programming.

Abstract: A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of −5˜−7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes electrons to be injected from a source 116 and a drain 117 into the channel (P-type well 123) (a). As the voltage applied to the P-type well 123 changes to −5 V, a depletion layer 124 is formed at the channel. At the depletion layer 124, the electrons are accelerated toward a tunnel oxide film 111 (b). The electrons having been accelerated in the channel are injected into the tunnel oxide film 111, are allowed to move inside the tunnel oxide film 111 by the electrical field at the tunnel oxide film 111 and are finally trapped at a floating gate 113.

Abstract: A method of erasing a flash memory device performs erase operation by hot carrier injection method, by applying a ground potential to a source and applying the bias from a high voltage to a low voltage step by step, with a voltage of 5V being applied to a drain, wherein the bias of a floating gate in the flash memory device keeps 1.8 through 2V. being hot carrier injection condition and wherein the gate bias adjusts the bias applied according to the coupling ratio. Thus, it can reduce the erase time and allows the erase on a byte basis.

Abstract: The present invention provides a method for writing data to a non-volatile semiconductor memory device including a plurality of memory cells which are arranged in a matrix in which data can be electrically written to or erased from the memory cells, the plurality of memory cells being grouped into one or more blocks, the memory cells in each block being provided on a same semiconductor base, each of the memory cells having a field effect transistor including a drain, a source, a floating gate and a control gate, the sources of the memory cells in each block being electrically connected to each other.

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract: In a transistor including first and second diffused layers of a second conductance, opposite to each other through a channel region of a first conductance type, and a two-storied gate electrode on the channel region of the first conductance type, a channel region and one of the diffused layers are set at a first voltage level; the other thereof is set at a second voltage level; a control gate is set at the first or a third voltage level; a difference between the first and second voltage levels is set larger in absolute value than that between the first and third voltage levels; and a part of charges flowing in the channel region with respect to the transistor flowing a channel current is injected into the floating gate. This solves difficulties of large driving currents at write back, a long write back time, deterioration of channel conductance, and the like.

Abstract: The present invention provides a floating gate field effect transistor having a floating gate electrode and a control gate electrode, wherein a low impurity concentration layer of a first conductivity type extends between source and drain regions and in an upper region of a semiconductor region of the first conductivity type, and the low impurity concentration layer is lower in impurity concentration than the semiconductor region, and a channel region is formed in the low impurity concentration layer when the floating gate field effect transistor turns ON.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.