Abstract: A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.

Abstract: The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.

Abstract: In a semiconductor memory device the potential of a semiconductor substrate and that of all of a plurality of word lines are increased to an erase voltage by means of a boosting circuit, and subsequently the potential of the word line selected by a word line selection circuit is decreased, when data of a memory cell is erased.

Abstract: A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of erasing the memory cell by withdrawing negative charge from a floating gate therein using a positive control electrode bias and a negative substrate bias. The use of a negative substrate bias increases the potential difference between the control electrode and the floating gate and this increase results in faster and more reliable erasing. A step is also performed to program the memory cell by accumulating negative charge on the floating gate using a positive control electrode bias, a negative substrate bias and a positive drain bias. Here, the negative substrate bias is used advantageously to reduce the likelihood that non-selected memory cells will become inadvertently programmed during operations to program selected memory cells.

Abstract: A method of operating a flash memory structure including a programming step. The method includes providing a flash memory device, the flash memory device comprising a substrate of first conductivity type, a source region of second conductivity type being defined in the substrate and a drain region of second conductivity type defined in the substrate. The flash memory device can be a split gate, a stacked gate, or other type of physical structure. The method includes applying a drain voltage of first polarity type on the drain region and applying a control gate voltage of a first conductivity type on the control gate. The method also includes applying a source voltage of second polarity type ranging from about 0.1 volt to about 0.5 volt on the source region, while maintaining a ground potential on the substrate to inject electrons onto a floating gate to program the floating gate.

Abstract: A method is provided to increase the speed of a non-volatile memory transistor by increasing the read channel current in the non-volatile memory transistor. This increase in speed is accomplished without increasing the VCC voltage supply source or decreasing the channel length of the non-volatile memory transistor. The increase in read channel current is accomplished by applying a low voltage to the substrate region of the non-volatile memory transistor, while grounding the source of the non-volatile memory transistor. If the non-volatile memory transistor is located in an array, the low voltage is applied to the sources and drains of non-volatile memory transistors on unselected bit lines to inhibit junction leakage channel current from these unselected non-volatile memory transistors.

Abstract: A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of −5˜−7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes electrons to be injected from a source 116 and a drain 117 into the channel (P-type well 123) (a). As the voltage applied to the P-type well 123 changes to −5 V, a depletion layer 124 is formed at the channel. At the depletion layer 124, the electrons are accelerated toward a tunnel oxide film 111 (b). The electrons having been accelerated in the channel are injected into the tunnel oxide film 111, are allowed to move inside the tunnel oxide film 111 by the electrical field at the tunnel oxide film 111 and are finally trapped at a floating gate 113.

Abstract: A circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk is disclosed. The control circuit comprises a voltage source, a first charge-pumping circuit, a word-line switch, a second charge-pumping circuit, a source switch, a third charge-pumping circuit, and a bulk switch. The first charge-pumping circuit, second charge-pumping circuit and third charge-pumping circuit respectively generate a first positive voltage, second positive voltage and negative voltage in response to the voltage source. The word-line switch selects and applies one of the voltage source or the first positive voltage to the control gate. The source switch selects and applies one of a ground potential or the second positive voltage to the source. The bulk switch selects and applies one of the ground potential or the negative voltage to the bulk.

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A method of Chisel programming in non-volatile memory by source bias. Whereby when reading and/or programming operations are executed, a body reading voltage and a body programming voltage are used. The method is comprised of changing the body programming voltage to reduce the difference between the changed body programming voltage and the body reading voltage and then running the programming operation utilizing the changed body programming voltage. Advantages include: elimination of the negative effects of parasitic capacitors in memory cells, simplification of bias circuit design, enhanced device reliability, and reduced disturbance.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: A non-volatile memory cell is formed in a semiconductor substrate and includes a control gate and a floating gate formed over said semiconductor substrate. A first active region and a second active region formed in said substrate. A first implant region formed in said substrate, said first implant region contiguous to said first active region and a second implant region formed in said substrate, said second implant region contiguous to said second active region. A channel region separates said first implant region and said second implant region. In a further aspect, a method of programming and erasing a non-volatile memory cell is disclosed. Programming of said cell is accomplished by injecting hot carriers into a floating gate through a first area of an oxide layer by capacitively coupling said floating gate to a substrate. Erasing said cell is accomplished by injecting oppositely charged hot carriers into said floating gate through a second area of said oxide layer.

Abstract: There is provided a storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the area via a gate insulating film, and a control gate formed on the floating gate via an interlayer insulating film, the method comprising steps of: applying a predetermined positive voltage to a bit line connected to the drain area and a word line connected to the control gate, injecting an electron to the floating gate, and writing data to a selected memory cell; applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to the semiconductor substrate or the source area, discharging the electron accumulated in the floating gate of the selected memory cell, and performing data erasing; and after the data erasing, applying the predetermined positive voltage necessary for injecting the electron to the floating gate from a channel area in the vicinity o

Abstract: A method for extracting a channel length between a source and a drain in a substrate of a transistor is disclosed herein. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase. The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.

Abstract: A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.

Abstract: At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to VL slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.

Abstract: In a nonvolatile semiconductor memory device using a stacked gate structure type transistor as a memory cell, an N-type well is formed on the surface of a P-type silicon substrate, and a plurality of P-type wells are formed on the surface of the N-type well. The P-type wells are electrically isolated by trenches. A plurality of memory cells are formed on each of the P-type wells, and a P-type contact layer, which is connected to a bias circuit, is formed thereon. When information is read, a reverse bias voltage is selectively applied by the bias circuit between the P-type silicon substrate and the P-type well not including an N-type source diffusion layer of a selected memory cell.

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

Abstract: A method of erasing a flash memory in accordance with the present invention comprises: pre-programming to allow all memory cells to have the same threshold voltage; pre-programming verification for verifying whether the pre-programming is successfully executed; erasing memory cells; erasing verification for verifying whether said erasing is successfully executed; recovering over-erased cells, wherein the recovering step is performed under multiple voltages are sequentially applied to the substrate of the over-erased memory cells; and recovery verification for verifying whether the recovery step is successfully executed.

Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout. Both are divided into blocks of cells formed in substrate regions isolated from one another. In the second matrix, the information is organized in pages each contained in a row of memory cells of one of the blocks of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of a polarity opposite to the supply voltage of the device is applied during an erasing phase to a single wordline selected by the row decoder, to page-erase the information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block.

Abstract: A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

Abstract: A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By eliminating the need to pre-program the memory array with hot electrons, the invention provides a signicant improvement for flash arrays, because device life and reliability is extended. In addition, pre-programming time and power is reduced significantly since the operation takes place on a sector (parallel) basis rather than a single bit line (serial) basis, and a charge pump is not needed to generate the current injected into floating gates of cells in the sector.

Abstract: An integrated circuit has a memory array comprising memory devices formed in a multiplicity of electrically isolated semiconductor regions that share a common set of bit lines. A given semiconductor region, typically a tub, is biased to a given voltage if a memory cell formed in that tub is accessed for a write operation, and biased to another voltage at other times. Although there may be many memory devices along the same bit line, during programming only the memory devices in the selected tub will be disturbed by the tub bias. Other memory devices residing in unselected tubs are protected against the bit line disturb. The present technique is especially advantageous when used with flash EEPROM memory cells that utilize secondary electron injection to assist in programming the cells.

Abstract: A memory cell having a floating gate is formed on a semiconductor substrate of a first conduction type and is disposed in a region having a deep well of a second conduction type formed to a semiconductor substrate and a shallow well of a first conduction type formed in the deep well. An erasing operation of emitting electrons from floating gates is conducted utilizing a tunneling phenomenon by setting a control gate terminal to ground voltage and a source terminal S to VPP. The deep and shallow wells are supplied with VCC at time t1 and a source terminal is supplied with VPP at time t2 after a predetermined period of time from time t1 has elapsed.

Abstract: On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and electrically isolated, from the substrate, and a MOS transistor, used as a nonvolatile memory cell, forming a drain region and a source region respectively within the well layer is used as a memory cell. Well layers associated with different columns are connected to each other by a well wiring commonly so that operation voltage different from that of the semiconductor substrate is applied thereto. In the case of data erasing, prescribed positive voltage is applied to a well wiring, and prescribed voltage lower than said positive voltage is applied to a selected word line. In the case of data programming, prescribed negative voltage is applied to the well wiring, prescribed voltage higher than said negative voltage is applied to the selected word line.