Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.

Abstract: Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective well bias can be changed depending on whether a READ or WRITE operation is being conducted. In another aspect, cells in a memory circuit can be subjected to variable bias depending on conditions, such as, again, whether a READ or WRITE operation is underway.

Abstract: A semiconductor memory device includes a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor which has a drain connected to a source of the first MOS transistor. Each of the word lines connects commonly the control gates of the first MOS transistors in a same row. Each of the select gate lines connects commonly the gates of the second MOS transistors in a same row. The switch elements, in an erase operation, electrically connect the select gate lines to a semiconductor substrate in which the memory cell array is formed.

Abstract: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.

Abstract: The multiple bit, vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. The gate insulator may be a composite of oxide-nitride-aluminum oxide. The MOSFET is operated with either the first source/drain region or the second source/drain region serving as the source region, depending on the voltages applied to these regions. A negative substrate bias is applied during programming and erasing operations to enhance hot carrier injection.

Abstract: This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

Abstract: A speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a charge trapping dielectric layer of the memory cells.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

Abstract: P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic hole-electron pairs to be generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Various circuits incorporating such fuse or antifuse elements are also disclosed.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

Abstract: In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array that are to be programmed, all the electrodes of the cell are grounded. Then, an inhibiting voltage Vn is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or remain at the inhibiting voltage Vn. For all cells in the NVM array that are not selected for programming, the inhibiting voltage Vn is applied to Vr, Ve and Dr and is also applied to Vp, Dp and Vnw.

Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

Abstract: A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming voltage to the gate of the selected floating gate memory cells and coupling a program or program-inhibit voltage to program the selected floating gate memory cell(s) as desired. The use of a boosted tub programming approach avoids the requirement that the bitline and/or source line circuit design of the NAND Flash array be able to withstand or carry high voltages during programming of a floating gate memory cells and allows reuse of the block erase high voltage circuits connected to the substrate tub. This allows the NAND Flash memory array to be designed with smaller circuit designs and/or smaller circuit feature elements.

Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

Abstract: A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.

Abstract: A semiconductor device has: a main circuit including a plurality of MOS transistors operating at a first voltage; a memory requiring an operation at a second voltage higher than the first voltage; and a drive circuit for driving the memory, the drive circuit comprising one well, two or more MOS transistors in a cascade connection formed in the well, and well contact or contacts formed between MOS transistors in the well and on both outer sides of the cascade connection, or formed only between MOS transistors, or formed on both outer sides of the cascade connection, or formed only outside a drain of MOS transistors in the cascade connection. The semiconductor device is provided which integrates a memory requiring a high voltage, can simplify manufacture processes for a memory drive circuit and suppress an increase in an occupation area in chip of the memory drive circuit.

Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg?Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg?Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: Provided is concerned with a method of erasing a NAND flash memory device, capable of restraining an erasing disturbance fail arising from a deselected cell block and improving a product yield of the device by applying a negative voltage to a well of a high voltage transistor forming an X-decoder during an erasing operation in the NAND flash memory device.

Abstract: A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.

Abstract: Methods of erasing a non-volatile memory device having discrete charge trap sites between a semiconductor substrate and a gate include applying a negative voltage to a gate at least partially spaced apart from a semiconductor substrate by a charge storage layer providing discrete charge trap sites. A first positive voltage is applied to a source formed in the semiconductor substrate adjacent to one sidewall of the gate. A second positive voltage, which is equal to or less than the first positive voltage, is applied to a drain formed in the semiconductor substrate adjacent to the gate and located opposite the source.

Abstract: A charge injection method for improving the efficiency of generating hot carriers, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage layer of a memory transistor. A positive voltage is applied to the drain region by using a voltage of the source region as a reference, and a voltage having a polarity in accordance with charges to be injected is applied to a gate electrode. A voltage having a voltage value between a source voltage and a drain voltage for turning on a diode made by an N-type source region and a P-type body region is applied to the body region. Then a parasitic bipolar transistor turns on, and, consequently, impact ionization arises on the drain side and an injection charge amount increases.

Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

Abstract: Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

Abstract: The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

Abstract: A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: An array of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

Abstract: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.

Abstract: An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell is composed of a program transistor and read transistor with a control gate connected to a word line, a source connected the source select line, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The program transistor has a drain connected a first bit line and a read transistor has a drain connected to the second bit line. Each memory cell has a floating gate connector joining the floating gate of the read transistor to the floating gate of the read transistor. The nonvolatile memory device has a voltage controller that programs the each memory cell by programming the program transistor and reading the read transistor.

Abstract: The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.

Abstract: A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.

Abstract: A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.

Abstract: A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.

Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to

Abstract: A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.

Abstract: The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

Abstract: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.

Abstract: A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming voltage to the gate of the selected floating gate memory cells and coupling a program or program-inhibit voltage to program the selected floating gate memory cell(s) as desired. The use of a boosted tub programming approach avoids the requirement that the bitline and/or source line circuit design of the NAND Flash array be able to withstand or carry high voltages during programming of a floating gate memory cells and allows reuse of the block erase high voltage circuits connected to the substrate tub. This allows the NAND Flash memory array to be designed with smaller circuit designs and/or smaller circuit feature elements.

Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein. If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic hole-electron pairs to be generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Various circuits incorporating such fuse or antifuse elements are also disclosed.

Abstract: A nonvolatile memory cell occupying a minimum chip area including a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the cell structure so that one or more programmed states are determined. A semiconductor memory constructed by a large number of the nonvolatile memory cells can be obtained in a compact manner with simple and as few as possible steps. This process vertically stacked layers, and this semiconductor memory is thus easily to be combined with other integrated circuits on a single chip.