Abstract: A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.

Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.

Abstract: A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting terminal for application of a predetermined potential, and a third connecting terminal for application of a discharge signal. The circuit arrangement further includes a first switching element, having a load path and a control connection, the load path of which is connected between the first and second connecting terminals and a second switching element, having a load path and a control connection, the load path of which is connected between the first connecting terminal and a terminal for reference potential. The first switching element is driven in a manner dependent on a switching state of the second switching element. The second switching element is driven by a drive circuit to which the discharge signal is fed and which includes a comparator arrangement.

Abstract: An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

Abstract: The apparatus, systems, and methods described herein may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

Abstract: The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller also includes a voltage control circuit coupled to the temperature sensing circuit and configured to provide a bias voltage to at least one back-gate of the memory array based on the temperature.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.

Abstract: Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.

Abstract: A body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.

Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

Abstract: A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.

Abstract: A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an adjustable bias voltage circuit, and is coupled to a test circuit that generates a feedback signal indicating whether one or more of the memory cells fail to operate properly. The adjustable bias voltage circuit selectively adjusts a bias voltage tied to the substrate provided to the memory cells in response to the feedback signal to alter the operating characteristics of the memory cells so that all of the memory cells will operate properly. For some embodiments, a plurality of fuses are provided for storing control signals that control the bias voltage provided to the memory cells.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: Provided are a nonvolatile memory device and a method of operating the same, which have increased operation reliability and which facilitate increased integration. The nonvolatile memory device may include a semiconductor substrate, and at least one charge storage layer may be provided on a semiconductor substrate. At least one control gate electrode may be provided on the at least one charge storage layer. At least one first auxiliary gate electrode may be disposed on one side of and apart from the at least one charge storage layer and isolated from the semiconductor substrate.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers; and a charge storage layer formed in the insulating film. A direction from the first N-type diffusion layer to the second N-type diffusion layer is the same as a crystal orientation <100> of the P-type silicon layer. At the time of rewriting, the hot holes go over a potential barrier of the insulating film to be injected into the charge storage layer.

Abstract: A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MIS•FET for reading data, and a capacitance section. Gate electrodes of the MIS•FETs and a capacitance electrode of the capacitance section are constituted of part of the same floating gate electrode. A control gate electrode of the nonvolatile memory cell is formed of part of an n well to which the capacitance electrode is opposite.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

Abstract: A method of operating a memory array includes providing an array of memory cells arranged in rows and columns. Each column comprises a NAND unit cell including a plurality of memory cells coupled together serially. The plurality of memory cells of each NAND unit cell share a common well. The common well of each column is separated from common wells of adjacent columns by an isolation region. Each NAND unit cell includes a select gate transistor coupled to a memory cell in the column. A source of the select gate transistor is coupled to the common well of the NAND unit cell. The method includes accessing a first memory cell in a column by biasing the common well of the NAND unit cell of the first memory cell differently than the common well of other NAND unit cells are biased.

Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.

Abstract: Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.

Abstract: The semiconductor memory device comprising: an n-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region; and a gate electrode formed over the charge storage layer; a power supply circuit formed on the semiconductor substrate, the power supply circuit being connectable to the first diffused region, pumping a voltage supplied from an outside power supply and outputting the pumped voltage; and writing means which, upon writing to the n-channel memory cell transistor, applies a reference voltage to the second diffused region, and applies a negative voltage with respective to the reference voltage supplied from the power supply circuit to the first diffused region to thereby flow current between the first diffused region and the second diffused region and to store charges in the charge storage layer.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word lines crossing over the device isolation layers, and a multiple insulation layer intervened between the word line and the active region. The multiple insulation layer includes a charge trap insulation layer. A source/drain region is formed at each region defined by adjacent word lines and the adjacent device isolation layers. The source/drain regions have the same surface area. A write operation of the device comprises applying a first level voltage, a ground voltage, and a write voltage to one bit line, another bit line, and a selected word line, thereby writing data into a charge trap insulation layer. By changing the voltages applied to the bit lines, 2 bits may be stored in one memory cell.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region.

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Abstract: A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.

Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.

Abstract: The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

Abstract: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.

Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Abstract: An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

Abstract: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use fo a higher word line voltage, but help prevent an over soft programming effect.

Abstract: A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.