Abstract: A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.

Abstract: A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.

Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

Abstract: Operating NVM memory cell such as an NROM cell by using a combination of Fowler-Nordheim tunneling (FNT), hot hole injection (HHI), and channel hot electron (CHE) injection. In the FNT erase step, only a few cells may be verified, and in the CHE second programming step, the threshold voltage of those cells which were not fully erased in the FNT erase step is increased to a high threshold voltage level (ERS state).

Abstract: A variable resistance element (1) whose resistance changes with application of a voltage pulse is brought to a low resistance state by applying an erase pulse to a path shown by the broken line through selection of selection transistors. An erase pulse limiting resistance (2) is inserted in the broken-line path. The resistance value (Re) of the erase pulse limiting resistance (2) is set so that a first resistance value as the sum of all the ON resistance values of the selection transistors, Re and the wiring resistance in the path is equal to or more than a bulk resistance value of a thin film material used in the variable resistance element (1), to prevent the resistance of the variable resistance element (1) from decreasing to the bulk resistance value at which stable resistance change is not resumed.

Abstract: A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

Abstract: A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read transistor isolated within a well of the first conductivity type, and a floating gate overlying a portion of the control gate, the read transistor, and the first and second tunneling regions. The memory device is configured to be electrically programmed by changing a charge on the floating gate that changes the device threshold voltage. In one embodiment, the memory device is configured to be electrically programmed by applying a first potential between the first and second tunneling regions, and a second potential to the control gate, the second potential having a value less than the first potential.

Abstract: A semiconductor memory device is capable of reading data at a high speed, without using a reference cell transistor. The semiconductor memory device includes a sensing unit including first cross-coupled MOS transistors to sense and amplify a voltage difference between a first node and a second node, and a unit cell including second cross-coupled cell MOS transistors to latch data and output a first signal and a second signal corresponding to the latched data to the first node and the second node, respectively.

Abstract: A method of programming a multilevel cell flash memory includes dividing a memory cell array of the flash memory into a user block and a cache block, programming first LSB data into a page of the user block, programming first MSB data into the page of the user block after programming the first LSB data, programming second LSB data into a page of the cache block, and storing control data for controlling the flash memory in the cache block.

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

Abstract: A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.

Abstract: The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.

Abstract: An operating process of an organic device includes performing a programming process and an erasing process. The programming process includes steps of applying a first positive bias from the first electrode to the second electrode on the organic device so that a conductive state of the organic device is switched to be a first turn-on state when the organic device is in a turn-off state and applying a negative bias from the first electrode to the second electrode on the organic device so that the conductive state of the organic device is switched to be a second turn-on state when the organic device is in the first turn-on state. The erasing process includes a step of applying a second positive bias from the first electrode to the second electrode on the organic device so that the conductive state of the organic device is switched to be the turn-off state.

Abstract: Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell.

Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.

Abstract: The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel; and a gate structure formed on the ion-implanted layer. Via applying a bias voltage to the gate, the carrier density in the channel region is different from that in the source region or the drain region; thereby, the MOS device of the present invention can undertake programming, erasing and reading activities. The present invention can simplify the MOS device fabrication process, reduce the operating voltage, and promote the integration density of a 2-dimensional or 3-dimensional MOS device array.

Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

Abstract: A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on-one correspondence to the plural floating gates 11; a control gate 16 shared by the plural floating gates 11; a source 17 shared by the plural floating gates 11; and a drain 18 shared by the plural floating gates 11. Therefore, the FLOTOX EEPROM does not encounter the decrease of junction breakdown voltage of a drain region, allowing the application of sufficiently high write voltage. Further, cell area can be reduced.

Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.

Abstract: A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vcc to, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than Vcc. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage).

Abstract: A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.

Abstract: A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.

Abstract: A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided adjacent to the drain selecting line; and selecting a word line to program memory cells coupled to the selected word line to perform an even LSB program operation and an odd LSB program operation for the selected first word line. Each of the word lines is selected until all of the word lines have been selected, so that the even LSB program operation and the odd LSB program operation can be performed for all of the word lines. The even LSB program operation is performed to store a lower rank data bit in memory cells coupled to an even bit line assigned a selected word line.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency. The memory cell can comprise a dual gate structure, such that the cell is a 2-bit cell.

Abstract: Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program voltage, a voltage distributor coupled to the drain of the transistor, the voltage distributor configured to generate a distributor voltage, and a pumping clock controller configured to compare the distributor voltage to a reference voltage and to generate the pumping clock signal when the high voltage is less than a voltage substantially equal to the program voltage plus the threshold voltage of the transistor.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.

Abstract: A semiconductor memory device has first and second AF programming circuits having low and high AF programming threshold power supply voltages, respectively. In a process where a large majority of programming is carried out in the semiconductor memory device alone, the second AF programming circuit is used. In a module process where semiconductor devices having low withstand voltages are mounted in a module, the first AF programming circuit is used.

Abstract: Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page of a second group of memory cells to hold a second least significant bit. Once the lower page is programmed, the voltage may be shifted to the upper page of each memory cell into a final range representing one or more most significant bits to be programmed. Each memory cell may store a voltage within a final programmed range representing a binary value.

Abstract: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

Abstract: A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and write driver circuit store data bits to be programmed on the memory cell. The sense amplifier and write driver circuit drives the bit line through a program voltage during a program execution period when at least one bit from among the data bits to be programmed is a program data bit, and performs a verify read operation when a program verify code representing a verify read period corresponds to a state of the data bits to be programmed.

Abstract: A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

Abstract: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node.

Abstract: Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Abstract: A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The address of a selected cell that is to be programmed is received. A determination is made as to whether a selected wordline connected to the selected cell is located above or under a reference wordline based on the received address. The selected cell is programmed using local boosting when the selected wordline corresponds to the reference wordline or is located above the reference wordline. The selected cell is programmed using self-boosting when the selected wordline is located under the reference wordline. The programming method reduces circuit size of a nonvolatile memory device employing the programming method and efficiently prevents program disturbance due to charge sharing.

Abstract: A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

Abstract: The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure.

Abstract: A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted.

Abstract: A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.

Abstract: Embodiments relate to a method for measuring a threshold voltage of a flash device including inputting a voltage and a pulse width. The dependence of threshold voltage on the applied voltages and the pulse width may be determined by using a threshold voltage measuring equation, and equations regarding a plurality of device variables included within the threshold voltage measuring equation.

Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.

Abstract: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.

Abstract: A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.