Flash Patents (Class 365/185.33)
  • Patent number: 10978470
    Abstract: The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10970204
    Abstract: A RAID-enabled solid state drive (SSD) including: a controller connected to a plurality of channels; a plurality of flash chip groups, each including a plurality of flash chips coupled to the plurality of channels, the plurality of flash chips including: a plurality of non-parity flash chips; and i parity flash chips, wherein the controller is configured to write data to the plurality of flash chip groups such that within each of the plurality of flash chip groups only i or less flash chips of the plurality of flash chips are allowed to be written to at the same time, where i is an integer equal to 1 or more.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nima Elyasi, Changho Choi
  • Patent number: 10971240
    Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 6, 2021
    Inventors: Mohan Dunga, Pitamber Shukla
  • Patent number: 10943663
    Abstract: A method of programming a flash memory device includes selecting a first wordline of a plurality of wordlines to select a selected wordline, the selected wordline corresponding to a target memory cell and performing a programming loop. The programming loop includes applying a program voltage to the selected wordline and performing a verification to the target memory cell. The verification includes applying a pre-pulse voltage to the selected wordline, applying a plurality of pass voltages to unselected wordlines of the plurality of wordlines, after applying the pre-pulse voltage, applying a series of incremental verifying voltages to the selected wordline, and after applying the pre-pulse voltage, applying a floating voltage to a second wordline of the plurality of wordlines. The second wordline being adjacent to the selected wordline is programmed after the selected wordline.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yu Wang, Shuang Li, Khanh Nguyen, Chunyuan Hou, Qiang Tang
  • Patent number: 10908996
    Abstract: Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Ravi Motwani
  • Patent number: 10891057
    Abstract: There is disclosed a technique for use in optimizing write operations for flash devices. A system having a plurality of flash based solid state drives receives a write request to overwrite existing data stored on the solid state drives with new data. The write request data is formatted using a write granularity having a first size and the solid state drives are configured with a write granularity having a second size. Corresponding existing data is retrieved. The new data and the existing data are subdivided into multiple corresponding subunits where each subunit has a size equal to the second size. Each new data subunit is compared with each corresponding existing data subunit to identify which new data subunits include modified data. The new data subunits identified as having modified data are written to corresponding locations on the solid state drives.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: January 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Walter A. O'Brien, III, Steven A. Morley
  • Patent number: 10877689
    Abstract: The memory controller includes a register allocator for dividing one super block into a plurality of unit areas, a plurality of first counters each corresponding to a respective one of the plurality of unit areas, wherein each of the plurality of first counters increments a count value when a corresponding unit area is read accessed, a second counter corresponding to the super block, wherein the second counter increments a count value when a count value of any of the first counters reaches a first threshold value, and a command generator for generating a command for performing a read reclaim operation when the count value of the second counter reaches a second threshold value.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Se Hwa Jang
  • Patent number: 10846165
    Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, William C. Filipiak, Michael G. McNeeley, Kishore K. Muchherla, Sampath K. Ratnam, Akira Goda, Todd A. Marquart
  • Patent number: 10783971
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Patent number: 10783029
    Abstract: A storage system periodically replicates data to another storage system for data backup and protection. The storage system is configured to detect an irregularity potentially causing a fault in the storage system. Such a detected irregularity may a component failure in a storage device, a temperature change in a storage device, etc. In response to the detected irregularity, the storage system increases a replication rate of data to the backup storage system.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 22, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Stephen S. Huh, Ian Davies, Douglas William Dewey
  • Patent number: 10768852
    Abstract: A batch automatic test method and a batch automatic test device for solid state disks are provided. The batch automatic test method is used for testing a plurality of solid state disks by a batch automatic test device. The solid state disks are coupled to the batch automatic test device. The batch automatic test method includes the following steps. A plurality of buses of the batch automatic test device are scanned to mark the solid state disks and a system disk. A piece of disk information of each of the solid state disks is shown. Each of the pieces of the disk information includes a disk location of each of the solid state disks. A formatting procedure is synchronously performed on the solid state disks according to the disk locations. After performing the formatting procedure, a burn-in test procedure is automatically and synchronously performed on the solid state disks.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 8, 2020
    Assignees: SHENZHEN SHICHUANGYI ELECTRONICS CO., LTD, SILICON MOTION, INC.
    Inventors: Huang-Zhong Ni, Jun Cheng
  • Patent number: 10741256
    Abstract: A data storage system may include a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. Methods are also described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 10725668
    Abstract: A type of data relocation to perform on a group of solid state storage cells is selected from a group that includes garbage collection and wear leveling. Source blocks in the group of solid state storage cells are identified using the selected type of data relocation. The source blocks are read in order to obtain relocated data and the relocated data is stored in an open block in the group of solid state storage cells. Relocated data associated with the selected type of data relocation is stored in the open block and relocated data associated with the unselected type of data relocation is excluded from the open block.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Zheng Wu
  • Patent number: 10719437
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 10719237
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Patent number: 10719647
    Abstract: A method for generating FPGA-based prototype systems capable of implementing UFS HS-G4 communication protocols using inexpensive/slow FPGAs. ASIC/SoC-targeted circuit designs are modified to include a speed converter that causes a UFS controller to generate transmitted data streams at one-half operating speed (e.g., 146 MHz) during HS-G4 operations, modifies the transmitted data streams to intersperse filler data values between transmitted data values, and transmits the modified data streams to M-PHY physical interconnect devices (PIDs) at full speed (e.g., 292 MHz). The speed converter also receives full-speed HS-G4 data streams that include both data and filler values and causes the UFS controller to operate at one-half operating speed (e.g., 146 MHz) such that only data values are read. PLD-based prototype systems that include separate M-PHY PIDs mounted on PCBs are efficiently configured to implement the modified circuit design.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Ramesh Hanchinal, Sunil Raidurgam Venkat
  • Patent number: 10671297
    Abstract: A memory system may include: a nonvolatile memory device comprising K memory blocks; and a controller suitable for controlling an operation of the nonvolatile memory device. The controller may include: a counting management unit suitable for using K count codes capable of counting a preset range from a base value to a limit value in order to manage K counting values corresponding to predetermined operations of the K memory blocks, respectively, and adjusting the absolute values of the base value and the limit value using the count code in the form of a 1/N-chain depending on a distribution of the K counting values; and a wear-leveling operation unit suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in a section of values corresponding to 1/N of the preset range, the count code may be a J-based number, each of J and K may be a natural number larger than 2, and N may be any one of powers of J larger than 1.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Chang-Hyun Park
  • Patent number: 10636493
    Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Pitamber Shukla
  • Patent number: 10628081
    Abstract: In one embodiment, a method for reducing the variance in latency of host I/O commands by managing non-host command queues in a solid state storage drive comprises receiving a plurality of non-host commands in at least one non-host command queue, each of the plurality of non-host commands configured to be executed by one of a plurality of non-volatile memory dies, and issuing a non-host command from the at least one non-host command queue to one of the plurality of non-volatile memory dies when a latency-reducing condition is satisfied. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a present number of active non-host commands is less than a first maximum number of active non-host commands. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a latency cost of the non-host command is less than or equal to an available latency budget.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Steven Wells, Neil Buxton
  • Patent number: 10601449
    Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 24, 2020
    Assignee: INPHI CORPORATION
    Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
  • Patent number: 10585589
    Abstract: A data collation method in a storage array including reading first data from a first logical address without decompression, assigning, by a storage controller, a second logical address to the first data, storing the first data to the second logical address, establishing, by the storage controller, a mapping relationship between an address of a storage array and the second logical address, where the first logical address is mapped to a first physical address of a storage device, a length of the first physical address is equal to a length of first data, a length of the first logical address is equal to a length of second data, and the first data is compressed data of the second data, and receiving, by the storage controller, the first data from the storage device.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 10, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Mingchang Wei
  • Patent number: 10564898
    Abstract: A method and apparatus for managing storage devices includes a host interface, a plurality of storage device interfaces, and a processor. The host interface is configured to communicatively couple with a host device and the plurality of storage interfaces configured to communicatively couple with storage devices. The processor is communicatively coupled to the host interface and the plurality of storage device interfaces. Further, the processor is configured to receive requests from the host device via the host interface and communicate the requests to the storage devices via the plurality of storage device interfaces. The processor is additionally configured to receive responses from the storage devices via the plurality of storage interfaces and communicate the responses to the host device via the host interface, manage a global submission queue and a global completion queue, and manage a submission queue and a completion queue for each of the storage devices.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhijit Rao, Vinod Sasidharan
  • Patent number: 10566340
    Abstract: A semiconductor memory device includes a plurality of bit lines disposed over memory cells along a second direction intersecting with a first direction, and extending in the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed along the second direction over the bit lines, and extending in the first direction while being bent into zigzag shapes.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Chang-Man Son, Hyun-Soo Shin, Jae-Eun Jeon, Sung-Hyun Hwang
  • Patent number: 10552050
    Abstract: In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 4, 2020
    Assignee: BiTMICRO LLC
    Inventors: Marlon B. Verdan, Ricardo H. Bruce
  • Patent number: 10540242
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 21, 2020
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
  • Patent number: 10496472
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for using a combined parity buffer memory for multiple open blocks of non-volatile memory. A controller is configured to accumulate, to a memory buffer, combined parity data for multiple open blocks of non-volatile memory in response to write operations to the multiple open blocks of non-volatile memory. A controller is configured to determine to close one block of multiple open blocks of non-volatile memory. A controller is configured to generate non-combined parity data for a block of non-volatile memory based on write operations to multiple open blocks of non-volatile memory.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: December 3, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Raghavendra Gopalakrishnan
  • Patent number: 10489318
    Abstract: In an embodiment of the invention, an apparatus comprises: a first flash module comprising a first flash device; and a second flash module comprising a second flash device; wherein the first flash module and second flash module are coupled by a flash interconnect; wherein the first flash device is configured to store a first data stripe of a data and wherein the second flash device is configured to store a second data stripe of the data. In another embodiment of the invention, a method comprises: storing, in a first flash device in a first flash module, a first data stripe of a data; and storing, in a second flash device in a second flash module, a second data stripe of the data; wherein the first flash module and second flash module are coupled by a flash interconnect.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: November 26, 2019
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Avnher Villar Santos, Marlon Basa Verdan, Elsbeth Lauren Tagayo Villapana
  • Patent number: 10489085
    Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 26, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Alex Frolikov
  • Patent number: 10482988
    Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yueping Li
  • Patent number: 10482975
    Abstract: An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: November 19, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Luc Reboulet, James Walls
  • Patent number: 10475522
    Abstract: A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Yong Ju Kim, Do Sun Hong
  • Patent number: 10467093
    Abstract: Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
  • Patent number: 10446221
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Richard C. Murphy
  • Patent number: 10439650
    Abstract: Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 8, 2019
    Assignee: Quantum Corporation
    Inventor: George Saliba
  • Patent number: 10417122
    Abstract: Method and apparatus for data storage. In some embodiments, a solid-state memory includes an array of non-volatile memory cells arranged into erasable blocks. A register stores a multi-bit sequence value. A controller randomizes input data to be written to a selected erasable block by combining the input data with the multi-bit sequence value shifted by a number of bit locations responsive to an accumulated access count for the selected erasable block.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 17, 2019
    Assignee: Seagate Technology LLC
    Inventor: Nicholas Odin Lien
  • Patent number: 10410671
    Abstract: An information recording apparatus includes: a first memory which stores synchronization data for updating data on a recordable optical disc and/or adding data to the recordable optical disc; a second memory which stores erasure information indicating data to be erased; and a controller which controls addition, update, and erasure of data on the optical disc. The controller records the synchronization data onto the optical disc. After recording the synchronization data, the controller records, onto the optical disc, management information indicating the state of the optical disc on which the synchronization data has been recorded and the state of the optical disc resulting from erasure according to the erasure information. Subsequently, the controller closes the session. After closing the session, the controller physically erases the data to be erased which has been recorded on the optical disc.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshiaki Takasu, Takeharu Yamamoto, Akinori Yuba
  • Patent number: 10410726
    Abstract: There may be provided a semiconductor memory device including a memory cell array, an erase count storage unit, and a control logic. The memory cell array may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. The erase count storage unit may be configured to store an erase count value for each of the plurality of memory blocks. During an erase operation of a memory block, the erase operation may be performed based on the erase count value.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Hae Soo Kim
  • Patent number: 10403342
    Abstract: A memory system includes a code flash and data flash merged flash memory, which may contain a code flash with differential cell structure, a data flash with single cell structure, decoder circuitry, a sense amplifier, and other suitable support circuitry. The code flash and data flash may be located in a same plane or multi planes. In some examples, the code flash may be also accessed to read while the data flash is performing write operation, and vice versa.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Aspiring Sky Co. Limited
    Inventors: Zhijiong Luo, Shu Wang, Xiaoming Jin
  • Patent number: 10394479
    Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information on stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Deping He
  • Patent number: 10366752
    Abstract: Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 30, 2019
    Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD.
    Inventors: Misbah Ramadan, Shahar Kvatinsky, Ran Ginosar
  • Patent number: 10354743
    Abstract: A method of a memory system including memory regions includes performing error corrections for chunks in each of the memory regions, and computing trust levels corresponding respectively to the memory regions based on the error corrections, setting test-reading periods corresponding respectively to the memory regions, based on the trust levels for the memory regions, counting a number of normal-reading times for each of the memory regions, and managing access counts corresponding respectively to the memory regions based on the counted numbers and when an access count for a first memory region among the memory regions reaches a time corresponding to a test-reading period for the first memory region, performing one or more test-readings for the first memory region.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventor: Chan Woo Yang
  • Patent number: 10353599
    Abstract: A storage system includes a first storage unit including a first processor and a first array of node modules, each including a memory unit, and a second storage unit including a second processor and a second array of node modules, each including a memory unit. The first processor is configured to control the first and second storage units, and the second processor is configured to control the second storage unit and not the first storage unit when the first processor is set to control the first and second storage units, and control the first and second storage units, when the first processor is set to not control the second storage unit.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichiro Manabe
  • Patent number: 10347636
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 9, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10331938
    Abstract: A method for controlling unlocking includes the following operations. A reference feature point set of a finger of a user is acquired by scanning the finger using a fingerprint recognition sensor. A matching process is performed between the reference feature point set and at least one template feature point of a pre-stored fingerprint template feature point set in descending order of matching priority of the at least one template feature point. The terminal is unlocked based on the number of template feature points successfully matched with the reference feature point set.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 25, 2019
    Assignee: Guangdong Oppo Mobile Telecommunications Corp., Ltd.
    Inventor: Yibao Zhou
  • Patent number: 10310941
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 4, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Chih-Kang Yeh, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 10296452
    Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for determining a pool of blocks from the plurality of blocks as garbage collection (GC) victim block candidates based on a number of valid pages left in each of the plurality of blocks, and selecting a block from the pool of blocks having a minimum number of valid pages as a victim block for garbage collection.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng, Yunhsiang Hsueh
  • Patent number: 10297324
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • Patent number: 10290356
    Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Krishna K. Parat, Pranav Kalavade, Koichi Kawai, Akira Goda
  • Patent number: 10249383
    Abstract: A data storage device includes a nonvolatile memory device; and a control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails, wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Ju Hyeon Han, Jong Won Park, Chan Woo Yang
  • Patent number: 10241675
    Abstract: A method is provided for rebuilding a flash translation layer table of a solid state drive. The superblock includes plural superpages. Each of the plural superpages includes plural physical pages. The method includes steps of confirming if the flash translation layer table is lost or not after the solid state drive is powered on; if the flash translation layer table is lost, starting a superblock scanning method for determining a status of the superblock; and rebuilding the flash translation table according to the status of the superblock. The superblock scanning method includes steps of reading contents of a first physical page and a last physical page of a last superpage in the superblock, and determining a status of the superblock according to the contents of the first physical page and the last physical page.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: March 26, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yu-Chuang Peng, Min-I Hung