Flash Patents (Class 365/185.33)
  • Patent number: 11449271
    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
  • Patent number: 11422968
    Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 23, 2022
    Assignee: Infineon Technologies LLC
    Inventors: Clifford Zitlaw, Stephan Rosner
  • Patent number: 11348644
    Abstract: A memory device includes a cell string, a peripheral circuit and a control logic. The cell string includes a select transistor and a plurality of memory cells, and further includes a plurality of dummy cells, wherein the plurality of dummy cells are coupled in series between the select transistor and the plurality of memory cells. The peripheral circuit configured to perform a dummy program operation on the plurality of dummy cells. The control logic configured to control the peripheral circuit so that the plurality of dummy cells have different threshold voltage distributions during the dummy program operation.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Hoon Lee
  • Patent number: 11322223
    Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 11309049
    Abstract: The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access. A method for retrieving data from the memory component is also disclosed.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11282576
    Abstract: A memory device having an improved threshold voltage distribution includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform an erase operation on the memory block; and control logic configured to: control the peripheral circuit to suspend the erase operation in response to a suspend command received from an external source, determine an erase state of the plurality of memory cells by using a plurality of erase state verify voltages in response to a resume command received subsequently to the suspend command, and determine a level of an erase voltage to be applied to the memory block and an erase voltage applying time for which the erase voltage is to be applied based on the determination result.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Cho Rong Park, Cheol Joong Park
  • Patent number: 11276700
    Abstract: A semiconductor memory device includes first conductive layers stacked on a substrate; second conductive layers stacked on the substrate and apart from the first conductive layer in a direction; third conductive layers stacked on the substrate and electrically connected to the first and second conductive layers; first insulating layers arranged in the direction to sandwich the first conductive layers; second insulating layers arranged in the direction to sandwich the second conductive layers; slit regions that sandwich the third conductive layers; and memory pillars disposed on the first and second insulating layers. The slit region is disposed between an end portion of one of the first insulating layers and an end portion of one of the second insulating layers.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Keisuke Nakatsuka
  • Patent number: 11264104
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 11245420
    Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Seung Gu Ji
  • Patent number: 11237762
    Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 1, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Florian Longnos, Feng Yang, Wei Yang
  • Patent number: 11221766
    Abstract: During a power-on self-test (POST), the BIOS of an information handling system may read a percentage remaining of a persistent memory device. If the percentage remaining satisfies a threshold, the BIOS may provide a message recommending that the persistent memory device be replaced, or automatically swapping the namespaces between two sets of persistent memory devices based on the write endurance remaining threshold.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 11, 2022
    Assignee: Dell Products L.P.
    Inventors: Wei Liu, Ching-Lung Chao
  • Patent number: 11221945
    Abstract: A semiconductor memory device capable of smoothing the number of cycles of programming/erasing between blocks is provided. The semiconductor memory device includes: a memory cell array; an address translation table defining a relationship between logical address information and physical address information; an invalid block table managing the physical address information for identifying to-be-erased blocks of the blocks; a free block table managing the physical address information used for identifying erased usable blocks; an erasing element for erasing the blocks; a controller. When an erasing command and first logical address information are received from environment, the controller erases the block of the physical address information selected from the invalid block table, and rewrites the address translation table in a manner that the physical address information selected from the free block table corresponds to the first logical address information received from the external environment.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 11, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Norio Hattori
  • Patent number: 11157403
    Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Ki Duck Kim, Jea Young Zhang
  • Patent number: 11150812
    Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Reshmi Basu
  • Patent number: 11088617
    Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a control signal, wherein the control signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the control signal for providing the boosted intermediate voltage; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 11081150
    Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Gu Jo, Donggun Kim, Yong Ju Kim, Do-Sun Hong
  • Patent number: 11062775
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Patent number: 11055002
    Abstract: Methods for classifying data in a storage device are provided. A data classifier module in a controller calculates a placement factor of one or more streams of data associated with one or more logical block addresses based on a metadata update and recency count table. The data classifier module then classifies the one or more streams of data associated with one or more logical block addresses as hot, warm, or cold streams of data. Hot streams of data are routed to hot open memory blocks, warm streams of data are routed to warm open memory blocks, and cold streams of data are routed to cold open memory blocks. Routing streams of data to hot, warm, or cold open memory blocks results in more efficient garbage collection procedures and the reduction of block erasures.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 6, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhijit Rao, Vishwas Saxena
  • Patent number: 11048312
    Abstract: A system and method for controlling a SSD in response to a power failure event of a main power supply to the SSD. The method includes receiving and storing write commands and associated data payloads for execution on the SSD in volatile memory, detecting the power failure event on the SSD, supplying backup power to the SSD during the power failure event, and executing one or more write commands stored in the volatile memory by storing the associated data payloads in a non-volatile memory on the SSD using the backup power. In response to the execution, removing the one or more write commands from the cache such that one or more unexecuted write commands and the associated data payloads remain in the cache, and storing a list of the one or more unexecuted write commands, but not the associated data payloads, in non-volatile memory using the backup power.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Steven Wells, Robert Reed
  • Patent number: 11037640
    Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 15, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Ching-Huang Lu, Vinh Diep, Yingda Dong
  • Patent number: 11016705
    Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 25, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Huang Peng Zhang, Xiang Fu, Qi Wang
  • Patent number: 11010092
    Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 11003388
    Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 11, 2021
    Assignee: Microon Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 10991439
    Abstract: A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong Han, Jun Hyuk Lee
  • Patent number: 10978470
    Abstract: The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10971240
    Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 6, 2021
    Inventors: Mohan Dunga, Pitamber Shukla
  • Patent number: 10970204
    Abstract: A RAID-enabled solid state drive (SSD) including: a controller connected to a plurality of channels; a plurality of flash chip groups, each including a plurality of flash chips coupled to the plurality of channels, the plurality of flash chips including: a plurality of non-parity flash chips; and i parity flash chips, wherein the controller is configured to write data to the plurality of flash chip groups such that within each of the plurality of flash chip groups only i or less flash chips of the plurality of flash chips are allowed to be written to at the same time, where i is an integer equal to 1 or more.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nima Elyasi, Changho Choi
  • Patent number: 10943663
    Abstract: A method of programming a flash memory device includes selecting a first wordline of a plurality of wordlines to select a selected wordline, the selected wordline corresponding to a target memory cell and performing a programming loop. The programming loop includes applying a program voltage to the selected wordline and performing a verification to the target memory cell. The verification includes applying a pre-pulse voltage to the selected wordline, applying a plurality of pass voltages to unselected wordlines of the plurality of wordlines, after applying the pre-pulse voltage, applying a series of incremental verifying voltages to the selected wordline, and after applying the pre-pulse voltage, applying a floating voltage to a second wordline of the plurality of wordlines. The second wordline being adjacent to the selected wordline is programmed after the selected wordline.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yu Wang, Shuang Li, Khanh Nguyen, Chunyuan Hou, Qiang Tang
  • Patent number: 10908996
    Abstract: Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Ravi Motwani
  • Patent number: 10891057
    Abstract: There is disclosed a technique for use in optimizing write operations for flash devices. A system having a plurality of flash based solid state drives receives a write request to overwrite existing data stored on the solid state drives with new data. The write request data is formatted using a write granularity having a first size and the solid state drives are configured with a write granularity having a second size. Corresponding existing data is retrieved. The new data and the existing data are subdivided into multiple corresponding subunits where each subunit has a size equal to the second size. Each new data subunit is compared with each corresponding existing data subunit to identify which new data subunits include modified data. The new data subunits identified as having modified data are written to corresponding locations on the solid state drives.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: January 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Walter A. O'Brien, III, Steven A. Morley
  • Patent number: 10877689
    Abstract: The memory controller includes a register allocator for dividing one super block into a plurality of unit areas, a plurality of first counters each corresponding to a respective one of the plurality of unit areas, wherein each of the plurality of first counters increments a count value when a corresponding unit area is read accessed, a second counter corresponding to the super block, wherein the second counter increments a count value when a count value of any of the first counters reaches a first threshold value, and a command generator for generating a command for performing a read reclaim operation when the count value of the second counter reaches a second threshold value.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Se Hwa Jang
  • Patent number: 10846165
    Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, William C. Filipiak, Michael G. McNeeley, Kishore K. Muchherla, Sampath K. Ratnam, Akira Goda, Todd A. Marquart
  • Patent number: 10783029
    Abstract: A storage system periodically replicates data to another storage system for data backup and protection. The storage system is configured to detect an irregularity potentially causing a fault in the storage system. Such a detected irregularity may a component failure in a storage device, a temperature change in a storage device, etc. In response to the detected irregularity, the storage system increases a replication rate of data to the backup storage system.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 22, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Stephen S. Huh, Ian Davies, Douglas William Dewey
  • Patent number: 10783971
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Patent number: 10768852
    Abstract: A batch automatic test method and a batch automatic test device for solid state disks are provided. The batch automatic test method is used for testing a plurality of solid state disks by a batch automatic test device. The solid state disks are coupled to the batch automatic test device. The batch automatic test method includes the following steps. A plurality of buses of the batch automatic test device are scanned to mark the solid state disks and a system disk. A piece of disk information of each of the solid state disks is shown. Each of the pieces of the disk information includes a disk location of each of the solid state disks. A formatting procedure is synchronously performed on the solid state disks according to the disk locations. After performing the formatting procedure, a burn-in test procedure is automatically and synchronously performed on the solid state disks.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 8, 2020
    Assignees: SHENZHEN SHICHUANGYI ELECTRONICS CO., LTD, SILICON MOTION, INC.
    Inventors: Huang-Zhong Ni, Jun Cheng
  • Patent number: 10741256
    Abstract: A data storage system may include a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. Methods are also described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 10725668
    Abstract: A type of data relocation to perform on a group of solid state storage cells is selected from a group that includes garbage collection and wear leveling. Source blocks in the group of solid state storage cells are identified using the selected type of data relocation. The source blocks are read in order to obtain relocated data and the relocated data is stored in an open block in the group of solid state storage cells. Relocated data associated with the selected type of data relocation is stored in the open block and relocated data associated with the unselected type of data relocation is excluded from the open block.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Zheng Wu
  • Patent number: 10719237
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Patent number: 10719437
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 10719647
    Abstract: A method for generating FPGA-based prototype systems capable of implementing UFS HS-G4 communication protocols using inexpensive/slow FPGAs. ASIC/SoC-targeted circuit designs are modified to include a speed converter that causes a UFS controller to generate transmitted data streams at one-half operating speed (e.g., 146 MHz) during HS-G4 operations, modifies the transmitted data streams to intersperse filler data values between transmitted data values, and transmits the modified data streams to M-PHY physical interconnect devices (PIDs) at full speed (e.g., 292 MHz). The speed converter also receives full-speed HS-G4 data streams that include both data and filler values and causes the UFS controller to operate at one-half operating speed (e.g., 146 MHz) such that only data values are read. PLD-based prototype systems that include separate M-PHY PIDs mounted on PCBs are efficiently configured to implement the modified circuit design.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Ramesh Hanchinal, Sunil Raidurgam Venkat
  • Patent number: 10671297
    Abstract: A memory system may include: a nonvolatile memory device comprising K memory blocks; and a controller suitable for controlling an operation of the nonvolatile memory device. The controller may include: a counting management unit suitable for using K count codes capable of counting a preset range from a base value to a limit value in order to manage K counting values corresponding to predetermined operations of the K memory blocks, respectively, and adjusting the absolute values of the base value and the limit value using the count code in the form of a 1/N-chain depending on a distribution of the K counting values; and a wear-leveling operation unit suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in a section of values corresponding to 1/N of the preset range, the count code may be a J-based number, each of J and K may be a natural number larger than 2, and N may be any one of powers of J larger than 1.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Chang-Hyun Park
  • Patent number: 10636493
    Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Pitamber Shukla
  • Patent number: 10628081
    Abstract: In one embodiment, a method for reducing the variance in latency of host I/O commands by managing non-host command queues in a solid state storage drive comprises receiving a plurality of non-host commands in at least one non-host command queue, each of the plurality of non-host commands configured to be executed by one of a plurality of non-volatile memory dies, and issuing a non-host command from the at least one non-host command queue to one of the plurality of non-volatile memory dies when a latency-reducing condition is satisfied. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a present number of active non-host commands is less than a first maximum number of active non-host commands. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a latency cost of the non-host command is less than or equal to an available latency budget.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Steven Wells, Neil Buxton
  • Patent number: 10601449
    Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 24, 2020
    Assignee: INPHI CORPORATION
    Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
  • Patent number: 10585589
    Abstract: A data collation method in a storage array including reading first data from a first logical address without decompression, assigning, by a storage controller, a second logical address to the first data, storing the first data to the second logical address, establishing, by the storage controller, a mapping relationship between an address of a storage array and the second logical address, where the first logical address is mapped to a first physical address of a storage device, a length of the first physical address is equal to a length of first data, a length of the first logical address is equal to a length of second data, and the first data is compressed data of the second data, and receiving, by the storage controller, the first data from the storage device.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 10, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Mingchang Wei
  • Patent number: 10564898
    Abstract: A method and apparatus for managing storage devices includes a host interface, a plurality of storage device interfaces, and a processor. The host interface is configured to communicatively couple with a host device and the plurality of storage interfaces configured to communicatively couple with storage devices. The processor is communicatively coupled to the host interface and the plurality of storage device interfaces. Further, the processor is configured to receive requests from the host device via the host interface and communicate the requests to the storage devices via the plurality of storage device interfaces. The processor is additionally configured to receive responses from the storage devices via the plurality of storage interfaces and communicate the responses to the host device via the host interface, manage a global submission queue and a global completion queue, and manage a submission queue and a completion queue for each of the storage devices.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhijit Rao, Vinod Sasidharan
  • Patent number: 10566340
    Abstract: A semiconductor memory device includes a plurality of bit lines disposed over memory cells along a second direction intersecting with a first direction, and extending in the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed along the second direction over the bit lines, and extending in the first direction while being bent into zigzag shapes.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Chang-Man Son, Hyun-Soo Shin, Jae-Eun Jeon, Sung-Hyun Hwang
  • Patent number: 10552050
    Abstract: In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 4, 2020
    Assignee: BiTMICRO LLC
    Inventors: Marlon B. Verdan, Ricardo H. Bruce
  • Patent number: 10540242
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 21, 2020
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
  • Patent number: RE48983
    Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto