Erase Patents (Class 365/185.29)
  • Patent number: 12198770
    Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 14, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Tzu-Hsuan Hsu, Chen-Huan Chen, Ken-Hui Chen
  • Patent number: 12198767
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
  • Patent number: 12190959
    Abstract: Aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. The processor accesses a configuration register to identify a quantity of memory slices to erase. The processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: January 7, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Phil Reusswig
  • Patent number: 12183396
    Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol, Tomoko Ogura Iwasaki
  • Patent number: 12183402
    Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 31, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Seo, Yong-Wan Son, Dogyeong Lee, Youngha Choi
  • Patent number: 12176018
    Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: December 24, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huan Lu
  • Patent number: 12158806
    Abstract: A controller includes an interface and a processor. The interface communicates with memory cells. The processor reads a Code Word (CW) from the memory cells using read thresholds to produce respective readouts, the read thresholds defining zones, identifies a subgroup of the memory cells associated with zones positioned about a Read Voltage (RV) predetermined between adjacent first and second Programming Voltages (PVs), estimates for each zone, based on the readouts, first and second cumulative counts of the memory cells corresponding to the first and second PVs, models first and second PDFs associated respectively with the memory cells programmed to the first and second PVs, based on the first and second cumulative counts, calculates for the zones respective reliability measures, based on the first and second PDFs, and assigns the reliability measures to bits of the CW, and decodes the CW by applying soft decoding to the assigned reliability measures.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: December 3, 2024
    Assignee: APPLE INC.
    Inventors: Yonathan Tate, Amit Pinchas Aylon
  • Patent number: 12131053
    Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: October 29, 2024
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 12131784
    Abstract: A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 29, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwon Park, Bongsoon Lim, Byungsoo Kim
  • Patent number: 12100443
    Abstract: A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: September 24, 2024
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Koji Sakui, Riichiro Shirota, Nozomu Harada
  • Patent number: 12087364
    Abstract: A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 10, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masafumi Hayakawa
  • Patent number: 12087365
    Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 10, 2024
    Assignee: Intel NDTM US LLC
    Inventor: Narayanan Ramanan
  • Patent number: 12080352
    Abstract: According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: September 3, 2024
    Assignee: Kioxia Corporation
    Inventors: Kyoka Konishi, Yasuyuki Ushijima, Hisaki Niikura, Eriko Akaihata
  • Patent number: 12073878
    Abstract: Disclosed is an electronic device which includes processing elements arranged in rows and columns, word lines connected with the rows of the processing elements, bit lines connected with the columns of the processing elements, body lines connected with the columns of the processing elements, and source lines connected with the rows of the processing elements. Each of the processing elements includes a first terminal connected with a corresponding bit line of the bit lines, a second terminal connected with a corresponding source line of the source lines, a control gate connected with a corresponding word line of the word lines, a floating gate between the control gate and a body, a body terminal connected with a corresponding body line of the body lines, and a capacitive element between the floating gate and the corresponding bit line.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: August 27, 2024
    Assignees: Samsung Electronics Co., Ltd., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Keewon Kwon, Sewon Yun, Sangwon Kim
  • Patent number: 12068033
    Abstract: Provided herein is a memory device that may include a plurality of memory cells coupled to a plurality of bit lines and a common source line. The memory device may also include a control circuit configured to control a peripheral circuit to perform a program operation that includes two or more program steps on selected memory cells of a selected word line. The peripheral circuit may be configured to perform a first program step of the two or more program steps on the selected memory cells, then perform a detrap operation that applies a detrap voltage to the plurality of bit lines and the common source line for a predefined time, and thereafter perform a second program step of the two or more program steps on the selected memory cells.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: August 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Woong Kim, Shin Won Seo, Dong Jae Jung
  • Patent number: 12068036
    Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: August 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiun-horng Lai, Pitamber Shukla, Ching-Huang Lu, Chengkuan Yin, Yoshiaki Fukuzumi
  • Patent number: 12057180
    Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: August 6, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Antonino Conte, Francois Maugain
  • Patent number: 12046648
    Abstract: A semiconductor with 3D flash memory storing cells includes a stack structure in each storing cell, a blocking layer, at least one floating gate layer, a tunnel dielectric layer, and a channel layer. The stack structure includes at least one control gate layer, at least one dielectric layer, and at least one erasing layer. The blocking layer is coplanar with the control gate layer. The floating layer is received in the blocking layer, and insulates the control gate layer by the blocking layers. The tunnel dielectric layer covers sides of the blocking layer and the floating gate layer. The channel layer is placed on a side of the tunnel electric layer. When the storing cell executes a data reading and writing process, a voltage is applied on the erasing layer to reduce a series resistance of the channel layer for rapid conduction by the semiconductor.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: July 23, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chung-Yi Chen
  • Patent number: 12040017
    Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: July 16, 2024
    Assignee: Weebit Nano Ltd.
    Inventor: Lior Dagan
  • Patent number: 12020753
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: June 25, 2024
    Assignee: Kioxia Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 12014059
    Abstract: A storage device, a method of operating the storage device, and a method of operating a host device are provided. The storage device includes a nonvolatile memory (NVM) and a storage controller controlling the nonvolatile memory. The storage controller is configured to receive a command from a host device giving instructions to sanitize data with the use of a cryptographic erase. The storage controller is also configured to, in response to a request from the host device, transmit to the host device a first verification value indicative of whether a first media encryption key (MEK) stored in the NVM has been deleted and a second verification value indicative of whether a second MEK, which is different from the first MEK, has been generated and stored in the NVM.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 18, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Jin Lee, Ji Soo Kim, Kyung-Woo Noh, Young Hyun Ji
  • Patent number: 12002515
    Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 4, 2024
    Assignee: Kioxia Corporation
    Inventors: Takumi Fujimori, Tetsuya Sunata, Masanobu Shirakawa, Hideki Yamada
  • Patent number: 11972809
    Abstract: A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 30, 2024
    Assignee: SanDisk Technologies, LLC
    Inventors: Sujjatul Islam, Yu-Chung Lien, Ravi Kumar, Xue Pitner
  • Patent number: 11967380
    Abstract: According to One embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: April 23, 2024
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11961565
    Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Ezra Edward Hartz
  • Patent number: 11961574
    Abstract: A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventors: June Young Choi, Un Sang Lee
  • Patent number: 11942161
    Abstract: A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: March 26, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Tse-Yen Liu
  • Patent number: 11929122
    Abstract: A memory device includes plural non-volatile memory cells and a control circuit. The plural non-volatile memory cells can store data and are arranged in series between a bit line and a source line. The control circuit synchronizes discharge of charges, which are accumulated in a channel formed by the plural non-volatile memory cells, through the bit line and the source line during an erase operation for erasing the data stored in the plural non-volatile memory cells.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Tae Heui Kwon
  • Patent number: 11915757
    Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 27, 2024
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Koji Sakui, Nozomu Harada
  • Patent number: 11915786
    Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: February 27, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Liang Qiao
  • Patent number: 11901015
    Abstract: The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 13, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xuan Tian, Liang Li
  • Patent number: 11894092
    Abstract: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoungho Son, Wontaeck Jung, Buil Nam
  • Patent number: 11875043
    Abstract: To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: January 16, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Toru Miwa
  • Patent number: 11862259
    Abstract: An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHINA FLASH CO., LTD. SHANGHAI
    Inventors: Hong Nie, Ying Sun
  • Patent number: 11837292
    Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 5, 2023
    Assignee: San Disk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang
  • Patent number: 11830559
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Noboru Shibata
  • Patent number: 11804429
    Abstract: There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11804269
    Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 31, 2023
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Hsuan Lin, Ming-Hsiu Lee
  • Patent number: 11798633
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Randy J. Koval, Hiroyuki Sanda
  • Patent number: 11783899
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: October 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
  • Patent number: 11756627
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 11756633
    Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshinao Suzuki, Haruka Shibayama
  • Patent number: 11726541
    Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11721402
    Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: August 8, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Nikhil Arora
  • Patent number: 11721404
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11721403
    Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 8, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: XiangNan Zhao, Yali Song, An Zhang, Hongtao Liu, Lei Jin
  • Patent number: 11688479
    Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
  • Patent number: 11664078
    Abstract: A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhipeng Dong, Li Xiang, Haiwen Fang, Min Zhang, Ling Chu, Haibo Li
  • Patent number: 11626170
    Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 11, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
  • Patent number: 11600322
    Abstract: A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 7, 2023
    Assignee: SK hynix Inc.
    Inventors: Byoung Young Kim, Jong Woo Kim, Young Cheol Shin