Erase Patents (Class 365/185.29)
  • Patent number: 10957411
    Abstract: A memory system includes a memory device including a plurality of blocks, each capable of storing data, and a controller, coupled with the memory device. The controller can perform at least one sub erase operation on each of the plurality of blocks, and variably increase an erase count of each of the plurality of blocks based on a timing of erasing data of each of the plurality of blocks through the sub erase operation.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10955470
    Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 23, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Brian Edward Foutz, Christos Papameletis, Vivek Chickermane, Krishna Vijaya Chakravadhanula
  • Patent number: 10949278
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for communicating error information during memory operations. For example, certain aspects of the present disclosure may provide a method for memory operations. The method generally including receiving a command from a host device, performing memory operations corresponding to the command received from the host device, detecting an error during the memory operations, and communicating the error based on the detection, wherein the error is communicated before receiving another command from the host device.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 16, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Asutosh Das, Vijay Viswanath, Ritesh Harjani, Srinivasan Karunelli
  • Patent number: 10949113
    Abstract: Techniques for profiling storage blocks in non-transitory memory (e.g., flash memory dies) to determine their retention capability, and assigning them with labels based on retention, are described. A superblock (SB) can be formed from physical blocks with the same labels located in different dies. The disclosed system and methods improve storage efficiency when the update frequency of stored data is non-uniform, as is typically the case. Moreover, the disclosed embodiments improve the reliability of solid state drives (SSDs), as well as reduce data refresh frequency and write amplification due to periodic refresh. A storage system can comprise a controller configured to obtain expected retention times for a plurality of storage blocks. The controller can partition the blocks into superblocks based on the retention times. A respective superblock is associated with a superblock retention time range, and contains blocks having expected retention times within the retention time range.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Yu Cai, Naveen Kumar, Aman Bhatia, Fan Zhang
  • Patent number: 10937492
    Abstract: A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Norio Hattori
  • Patent number: 10923195
    Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minkyung Bae, Tae Hun Kim, Myunghun Woo, Bongyong Lee, Doohee Hwang
  • Patent number: 10923197
    Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: February 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Ashish Baraskar, Vinh Diep
  • Patent number: 10916309
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 10910060
    Abstract: An apparatus comprising strings of non-volatile memory cells is disclosed. Each string comprises non-volatile memory cells, an operative select gate, and a dummy select gate. The apparatus comprises a select line connected to the operative select gate of each string, and a dummy line connected to the dummy select gate of each string. The dummy line is an immediate neighbor to the select line. The apparatus comprises a control circuit configured to apply a voltage waveform to the select line while the dummy line is floating. The control circuit is configured to detect a floating voltage on the dummy line while applying the voltage waveform to the select line. The control circuit is configured to determine a condition of the voltage waveform at a target location on the select line based on the floating voltage on the dummy line.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Jianzhi Wu, Xiang Yang
  • Patent number: 10910074
    Abstract: Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of iterations that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Se Chang Park
  • Patent number: 10896736
    Abstract: The present invention provides a semiconductor memory device capable of performing rapid erasing while reducing power consumption. In the flash memory of the present invention, the voltage of the P well is detected by the voltage detecting unit 200 during the erasing operation. When the voltage is lower than the threshold value, it is determined that the off leakage current of the selection transistor of the non-selection block is large, and the voltage of the global word line at the time of applying the next erase pulse is increased. When the voltage is above the threshold value, it is determined that the off leakage current is small, and the voltage of the global word line at the time of applying the next erase pulse is maintained.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 19, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Naoaki Sudo
  • Patent number: 10879266
    Abstract: A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector on the first channel layer, having a second doping concentration; a second stack on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a second conductive connector on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 29, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, I-Chen Yang
  • Patent number: 10875541
    Abstract: A vehicle control system includes: a first device that generates trajectory data indicating a future trajectory of a host vehicle and outputs the generated trajectory data; a second device that controls at least one of acceleration/deceleration and steering of the host vehicle on the basis of the trajectory data generated by the first device; and a third device that receives the trajectory data generated by the first device and writes the received trajectory data in a storage unit thereof, the third device being a device separate from at least the first device, wherein when an abnormality occurs in the trajectory data output by the first device, the second device controls at least one of acceleration/deceleration and steering of the host vehicle on the basis of the trajectory data which has been received by the third device and written in the storage unit before the abnormality occurred.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 29, 2020
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Masanori Takeda
  • Patent number: 10861571
    Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Yu-chung Lien
  • Patent number: 10847192
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Marie Takada, Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 10847226
    Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Jun Kim, Gae Hun Lee, Hea Jong Yang, Chan Lim, Min Kyu Jeong
  • Patent number: 10839864
    Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Hong Kwon, Young Sun Min, Dae Seok Byeon, Sung Whan Seo
  • Patent number: 10832793
    Abstract: In some examples, a defective memory cell detection circuitry is configured to provide a failure signal indicative of a failure of a sub-group of memory cells (e.g., a row of memory cells). The failure signal is generated responsive to the failure of a sense line to transition to one of a set of reference voltages within a threshold time from a memory command. In some examples, failure signals indicative of a failure of a sub-group of memory cells is used by vehicle computer control systems to operate a vehicle.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher S. Johnson
  • Patent number: 10832781
    Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Jae-Duk Lee
  • Patent number: 10825530
    Abstract: In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Jin Song, Hyun-Wook Park, Bong-Soon Lim, Do-Bin Kim
  • Patent number: 10811100
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 10790021
    Abstract: An EEPROM and methods for erasing, programming and reading it, the EEPROM includes a plurality of split-gate storage arrays, each of the plurality of split-gate storage cells including a source connected with a first bit line, a drain connected with a second bit line, a first control gate connected with a first store position, a word line gate connected with a word line and a second control gate connected with a second store position; and the first control gate is connected with a first control gate line, and the second control gate is connected with a second control gate line, wherein every N columns of the split-gate storage cells are formed on a first well structure, adjacent first well structures are separated by a second well structures having a different doping type with that of the first well structures, and N is a positive integer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 29, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Jian Hu
  • Patent number: 10777287
    Abstract: A memory control apparatus includes a randomizer configured to: randomize write data output from an arithmetic processing apparatus, and output the randomized write data to a memory; a derandomizer configured to: derandomize data read from the memory, and generate derandomized read data when a flag included in the data read from the memory indicates the randomized write data; and a selector configured to: select the derandomized read data and output the selected derandomized read data to the arithmetic processing apparatus when the flag indicates the randomized write data, and select the data read from the memory and output the selected read data to the arithmetic processing apparatus when the flag indicates deleted data.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Masayoshi Matsumura, Hiroshi Nakayama, Takao Matsui, Takashi Yamamoto, Yuka Hosokawa
  • Patent number: 10770117
    Abstract: A semiconductor storage device includes a source line, a first selection line, word lines, a dummy word line, and a second selection line. A first pillar having a first semiconductor layer extends through the first selection line, the word lines, and the first dummy word line and is connected to the source line. Memory cells are at intersections of the word lines and the first pillar. A conductive layer is on the first semiconductor layer and extends into the first dummy word line. A second pillar with a second semiconductor layer extends through the second selection line and contacts the conductive layer. A bit line is electrically connected to the second semiconductor layer. A control circuit is configured to apply voltages to the various lines during an erasing of the memory cells. A voltage between a source line voltage and a world line voltage is applied to dummy word line.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 10732857
    Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 4, 2020
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 10727243
    Abstract: A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Wei-Chen Chen
  • Patent number: 10720218
    Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ji-yoon Park, Wan-dong Kim, Seung-bum Kim, Deok-woo Lee, You-se Kim, Se-hwan Park, Jin-woo Park
  • Patent number: 10714497
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Mitsuteru Mushiga
  • Patent number: 10685715
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • Patent number: 10684785
    Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is less than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing n-bit information.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiko Fujii, Shigeo Homma, Junji Ogawa, Yoshinori Ohira
  • Patent number: 10672482
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 10658045
    Abstract: A method for programming memory blocks in a memory system includes identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system. The method also includes performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks. The method also includes storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks. The method also includes identifying, using the pre-erase table, at least one memory block to be programmed. The method also includes programming the at least one memory block by performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and performing a write operation on the at least one memory block.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 19, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Patent number: 10643712
    Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element determines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 5, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Makoto Senoo, Naoaki Sudo
  • Patent number: 10636483
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Miles Hirst, Hernan A. Castro, Stephen Tang
  • Patent number: 10636500
    Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. The discharge involves ramping up the word line voltages and grounding the ends of the NAND strings. To increase the discharge, a ramp up rate may be greater for the selected word line and for dummy memory cells adjacent to the interface, compared to the ramp up rate for the unselected word lines. In an option, the greater ramp up rate is also used for the word lines between the selected word line and the interface. In another option, the greater ramp up rate is used for the word lines in the same tier as the selected word line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Wei Zhao, Yingda Dong
  • Patent number: 10636699
    Abstract: A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said st
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: April 28, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Zongliang Huo
  • Patent number: 10622080
    Abstract: A non-volatile memory and its reading method are provided. The reading method includes: erasing a plurality of memory cells in a memory cell string; setting a target memory cell of the memory cells, setting an initial voltage, generating a plurality of programming voltages by gradually increasing the initial voltage based on a step value, sequentially performing a plurality of programming operations by the target memory cell according to the programming voltages, and verifying the target memory cell to obtain a first verifying current during the programming operations; setting a corresponding programming voltage as a target voltage through determining the first verifying current and a first reference current; and performing the programming operations on the memory cells other than the target memory cell according to the target voltage and setting the memory cell string as a reading reference memory cell string.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 14, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 10566048
    Abstract: Apparatus, systems, methods, and computer program products for managing refresh operations in memory devices are disclosed. An apparatus includes a memory device including a plurality of memory cells comprising an associated set of counters and a controller for the memory device. A controller is configured to randomly increment a counter associated with a memory cell in response to write disturbances for the memory cell. A controller is configured, in response to a counter being randomly incremented to a predetermined count, perform a refresh operation on a memory cell.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Minghai Qin, Won Ho Choi, Zvonimir Bandic
  • Patent number: 10559583
    Abstract: A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su Jin Park, Sun Young Kim, Jang Gn Yun
  • Patent number: 10553287
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 10510406
    Abstract: An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 17, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Huan-Ting Lin, Tsung-Yuan Huang, Wei-Hao Chen, Han-Wen Hu
  • Patent number: 10496782
    Abstract: According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Risho Koh, Mitsuru Miyamori, Katsumi Tsuneno
  • Patent number: 10438671
    Abstract: Techniques for reducing program disturb of memory cells which are formed in a two-tier stack, when a selected word line is in the upper tier. In one approach, at the start of the program phase of a program loop, voltages of word lines adjacent to the interface are increased to a pass voltage before voltages of remaining word lines are increased to a pass voltage. This delay provides time for residue electrons in the lower tier to move toward the drain end of a NAND string to reduce the likelihood of program disturb. In another approach, the voltages of the word lines adjacent to the interface are maintained at 0 V or other turn-off voltage during the program phase to block the passage of residue electrons from the lower tier to the upper tier.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 8, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10423337
    Abstract: A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventors: SeungGu Ji, HeeCheol Lee, YoungHo Kim
  • Patent number: 10403370
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 10388389
    Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 20, 2019
    Assignees: Silicon Storage Technology, Inc., The Regents Of The University of California
    Inventors: Xinjie Guo, Farnood Merrikh Bayat, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari
  • Patent number: 10373688
    Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 6, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Bogdan I. Georgescu, Gary P. Moscaluk, Vijay Raghavan, Igor G. Kouznetsov
  • Patent number: 10373690
    Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks; and a controller suitable for dividing the plurality of memory blocks into a first group and a second group, and controlling the memory blocks included the first group and the second group, respectively, wherein the controller is further suitable for: managing all operations except for an erase operation to the memory blocks of the first group through a first operation task; managing all operations except for an erase operation to the memory blocks of the second group through a second operation task; and managing the erase operation to the memory blocks of the first group and the memory blocks of the second group through an erase operation task.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10354733
    Abstract: Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: XILINX, INC.
    Inventors: Jindrich Zejda, Elliott Delaye, Ashish Sirasao, Yongjun Wu, Aaron Ng
  • Patent number: 10347339
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park