Erase Patents (Class 365/185.29)
  • Patent number: 11901015
    Abstract: The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 13, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xuan Tian, Liang Li
  • Patent number: 11894092
    Abstract: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoungho Son, Wontaeck Jung, Buil Nam
  • Patent number: 11875043
    Abstract: To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: January 16, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Toru Miwa
  • Patent number: 11862259
    Abstract: An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHINA FLASH CO., LTD. SHANGHAI
    Inventors: Hong Nie, Ying Sun
  • Patent number: 11837292
    Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 5, 2023
    Assignee: San Disk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang
  • Patent number: 11830559
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Noboru Shibata
  • Patent number: 11804269
    Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 31, 2023
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Hsuan Lin, Ming-Hsiu Lee
  • Patent number: 11804429
    Abstract: There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11798633
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Randy J. Koval, Hiroyuki Sanda
  • Patent number: 11783899
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: October 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
  • Patent number: 11756633
    Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshinao Suzuki, Haruka Shibayama
  • Patent number: 11756627
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 11726541
    Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Thomas H. Kinsley, Fuad Badrieh
  • Patent number: 11721404
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11721402
    Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: August 8, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Nikhil Arora
  • Patent number: 11721403
    Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 8, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: XiangNan Zhao, Yali Song, An Zhang, Hongtao Liu, Lei Jin
  • Patent number: 11688479
    Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
  • Patent number: 11664078
    Abstract: A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhipeng Dong, Li Xiang, Haiwen Fang, Min Zhang, Ling Chu, Haibo Li
  • Patent number: 11626170
    Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 11, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
  • Patent number: 11600322
    Abstract: A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 7, 2023
    Assignee: SK hynix Inc.
    Inventors: Byoung Young Kim, Jong Woo Kim, Young Cheol Shin
  • Patent number: 11594282
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: February 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 11581044
    Abstract: Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: February 14, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Changhyun Lee, Chao Zhang, Haibo Li
  • Patent number: 11557354
    Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 17, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Hsuan Lin, Ming-Hsiu Lee
  • Patent number: 11557341
    Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol, Tomoko Ogura Iwasaki
  • Patent number: 11551766
    Abstract: A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 11551739
    Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: January 10, 2023
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Liang Zhao
  • Patent number: 11538536
    Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: December 27, 2022
    Assignee: Kioxia Corporation
    Inventors: Shingo Nakazawa, Takashi Maeda
  • Patent number: 11487627
    Abstract: A storage device having improved data recovery performance includes a memory device including a first storage region and a second storage region, and a memory controller that controls the memory device. Before performing a write operation in the first storage region, the memory controller may backup data previously stored in the first storage region, based on a fail probability of the write operation to be performed in the first storage region. If the write operation fails, the previously-stored data may be recovered from where it was backed up.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Kyun Shin, Keun Hyung Kim
  • Patent number: 11443817
    Abstract: A nonvolatile memory device includes processing circuitry configured to apply a sub-voltage to the first word lines, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word lines, apply the sub-voltage to the second word lines, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word lines, apply the desired first read voltage to the first word lines while simultaneously reading the first memory cells connected to the first word lines, and apply the desired second read voltage different from the desired first read voltage to the second word lines while simultaneously reading the second memory cells connected to the second word lines.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoung-Won Yoon, Jae-Hak Yun, Jae Woo Im, Sang-Hyun Joo
  • Patent number: 11410735
    Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Patent number: 11386965
    Abstract: There are provided a memory device, a memory system including the memory device, and an operating method of the memory system. The memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a read operation by applying a read voltage to a selected memory block among the plurality of memory blocks, and control logic for controlling the peripheral circuit to perform a normal read operation using initially set voltages and a read retry operation using new read voltages. The peripheral circuit performs the read retry operation by using the new read voltage corresponding to program states other than at least one program state included in a specific threshold voltage region among a plurality of program states of the selected memory block.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 11380402
    Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Sik Kim, Dae Sung Kim
  • Patent number: 11373707
    Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 28, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Patent number: 11373718
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Hyun Hwang, Jin Haeng Lee
  • Patent number: 11367513
    Abstract: A system for recording HIPAA compliant medical imagery may be configured as follows. A medical imaging system comprising a special purpose computer. The special purpose computer comprising: a processor, a permanently installed hard drive, and a random access memory. The permanently installed hard drive is configured such that it stores all instructions necessary for the processor to process medical files transmitted from the first medical system. The permanently installed hard drive is further configured such that it stores all instructions necessary for the processor to encrypt and store all medical files, as they are created, on a removable drive only. The removable drive is an encrypted removable flash storage drive.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: June 21, 2022
    Assignee: GreatDef, Corp.
    Inventors: Marc Perez, Michael O'Leary
  • Patent number: 11361828
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Hwan Yun, Myeong Won Lee
  • Patent number: 11355198
    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: June 7, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Huai-Yuan Tseng, Sarath Puthenthermadam
  • Patent number: 11342030
    Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: May 24, 2022
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventor: Ming-Xun Wang
  • Patent number: 11315914
    Abstract: A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Sung, Young Ki Kim, Jin Ho Kim, Byung Hyun Jun
  • Patent number: 11289132
    Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 29, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Chieh Cheng, Yin-Jen Chen
  • Patent number: 11276471
    Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
    Type: Grant
    Filed: March 20, 2021
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Hwan Park, Wan-Dong Kim
  • Patent number: 11276708
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Mitsuteru Mushiga
  • Patent number: 11257554
    Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 11232839
    Abstract: Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: January 25, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Changhyun Lee, Chao Zhang, Haibo Li
  • Patent number: 11211396
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 11205481
    Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
  • Patent number: 11164885
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Ju Ry Song, Se Ho Lee, Jae Gil Lee
  • Patent number: 11158392
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11158381
    Abstract: An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-sang Lee
  • Patent number: 11152367
    Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shyng-Yeuan Che, Shih-Ping Lee, Bo-An Tsai