Erase Patents (Class 365/185.29)
  • Patent number: 11443817
    Abstract: A nonvolatile memory device includes processing circuitry configured to apply a sub-voltage to the first word lines, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word lines, apply the sub-voltage to the second word lines, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word lines, apply the desired first read voltage to the first word lines while simultaneously reading the first memory cells connected to the first word lines, and apply the desired second read voltage different from the desired first read voltage to the second word lines while simultaneously reading the second memory cells connected to the second word lines.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoung-Won Yoon, Jae-Hak Yun, Jae Woo Im, Sang-Hyun Joo
  • Patent number: 11410735
    Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Patent number: 11386965
    Abstract: There are provided a memory device, a memory system including the memory device, and an operating method of the memory system. The memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a read operation by applying a read voltage to a selected memory block among the plurality of memory blocks, and control logic for controlling the peripheral circuit to perform a normal read operation using initially set voltages and a read retry operation using new read voltages. The peripheral circuit performs the read retry operation by using the new read voltage corresponding to program states other than at least one program state included in a specific threshold voltage region among a plurality of program states of the selected memory block.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 11380402
    Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Sik Kim, Dae Sung Kim
  • Patent number: 11373707
    Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 28, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Patent number: 11373718
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Hyun Hwang, Jin Haeng Lee
  • Patent number: 11367513
    Abstract: A system for recording HIPAA compliant medical imagery may be configured as follows. A medical imaging system comprising a special purpose computer. The special purpose computer comprising: a processor, a permanently installed hard drive, and a random access memory. The permanently installed hard drive is configured such that it stores all instructions necessary for the processor to process medical files transmitted from the first medical system. The permanently installed hard drive is further configured such that it stores all instructions necessary for the processor to encrypt and store all medical files, as they are created, on a removable drive only. The removable drive is an encrypted removable flash storage drive.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: June 21, 2022
    Assignee: GreatDef, Corp.
    Inventors: Marc Perez, Michael O'Leary
  • Patent number: 11361828
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Hwan Yun, Myeong Won Lee
  • Patent number: 11355198
    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: June 7, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Huai-Yuan Tseng, Sarath Puthenthermadam
  • Patent number: 11342030
    Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: May 24, 2022
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventor: Ming-Xun Wang
  • Patent number: 11315914
    Abstract: A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Sung, Young Ki Kim, Jin Ho Kim, Byung Hyun Jun
  • Patent number: 11289132
    Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 29, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Chieh Cheng, Yin-Jen Chen
  • Patent number: 11276708
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Mitsuteru Mushiga
  • Patent number: 11276471
    Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
    Type: Grant
    Filed: March 20, 2021
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Hwan Park, Wan-Dong Kim
  • Patent number: 11257554
    Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 11232839
    Abstract: Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: January 25, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Changhyun Lee, Chao Zhang, Haibo Li
  • Patent number: 11211396
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 11205481
    Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
  • Patent number: 11164885
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Ju Ry Song, Se Ho Lee, Jae Gil Lee
  • Patent number: 11158392
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11158381
    Abstract: An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-sang Lee
  • Patent number: 11152367
    Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shyng-Yeuan Che, Shih-Ping Lee, Bo-An Tsai
  • Patent number: 11150808
    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: October 19, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 11133074
    Abstract: Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Weihao Wang, Xiaohua Liu, David Joaquin Reed
  • Patent number: 11121144
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
  • Patent number: 11114498
    Abstract: An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal. A reference signal generation unit generates a reference signal being a signal serving as a reference used when conversion from an analog image signal output from the image signal output unit into a digital image signal is performed.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 7, 2021
    Assignee: SONY CORPORATION
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 11107537
    Abstract: A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 31, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su Chang Jeon, Seung Bum Kim, Ji Young Lee
  • Patent number: 11094381
    Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.
    Type: Grant
    Filed: June 2, 2019
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventors: Muhammad N. Ashraf, Alexander Paley, Yuhua Liu, Vadim Khmelnitsky, Matthew J. Byom
  • Patent number: 11094380
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 17, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 11081197
    Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Yu-Chung Lien
  • Patent number: 11074979
    Abstract: The erase voltage controlled with higher accuracy than the related art when erasing data in a non-volatile semiconductor memory device is provided. An control circuit for controlling an erase voltage includes: a slope adjustment circuit that controls a slope having a step shape by controlling a step voltage, a target voltage, and a step width of the erase voltage. The slope adjustment circuit repeatedly increases the erase voltage by the step voltage for each predetermined clock pulse control signal to the target voltage based on the step voltage and the target voltage, and outputs the clock pulse control signal to the erase voltage generation circuit by repeatedly clocking each time interval corresponding to the step width based on the step width.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 27, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Mathias Yves Gilbert Bayle
  • Patent number: 11056211
    Abstract: Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Aneesh Puthoor, Harvijay Singh, Narendhiran Chinnaanangur Ravimohan
  • Patent number: 11049573
    Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 29, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rieko Funatsuki, Takashi Maeda, Hidehiro Shiga, Hiroshi Maejima
  • Patent number: 11049868
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Nagashima, Tatsuya Kato, Wataru Sakamoto
  • Patent number: 11049567
    Abstract: A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 29, 2021
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventor: Michael Peeters
  • Patent number: 11049568
    Abstract: Gate-induced leakage current that is independent of a location of a physical p-n junction between a semiconductor channel and a source/drain region can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit that is activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a vertically-neighboring pair of electrically conductive layers with a depletion region therebetween. The depletion region can generate and inject majority charge carriers into the semiconductor channel during the erase operation. The depletion region can be formed in the source region or in the drain region and may not overlap with a physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Shinsuke Yada
  • Patent number: 11037632
    Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 15, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Chih-Chieh Cheng, Cheng-Hsien Cheng, Yu-Hung Huang, Atsuhiro Suzuki, Wen-Jer Tsai
  • Patent number: 11036544
    Abstract: A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sng-Hoon Park, In-Soo Kim, Jong-Won Kim, Sang-Kwon Moon
  • Patent number: 11031086
    Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Moon Sik Seo
  • Patent number: 11031063
    Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ali Taghvaei, Atul Katoch
  • Patent number: 11029714
    Abstract: A tracking voltage generator, the latter including: a first transistor having a first leakage current and which is coupled with the flipped gate transistor so that a difference between a gate-source voltage (Vgs) of a flipped gate transistor and the first transistor is approximately equal to a bandgap voltage of a semiconductor material from which the tracking voltage generator is formed; an output node providing a tracking voltage which has a positive or negative temperature dependency based on the flipped gate transistor and the first transistor; and a second transistor connected to the output node and which has a second leakage current. A current reference includes: the tracking voltage generator; an amplifier to receive the tracking voltage and output an amplified signal; a control transistor to receive the amplified signal and conduct a reference current therethrough; and a control resistor connected in series with the control transistor.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mohammad Al-Shyoukh, Alexander Kalnitsky
  • Patent number: 11011240
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 18, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Patent number: 10955470
    Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 23, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Brian Edward Foutz, Christos Papameletis, Vivek Chickermane, Krishna Vijaya Chakravadhanula
  • Patent number: 10957411
    Abstract: A memory system includes a memory device including a plurality of blocks, each capable of storing data, and a controller, coupled with the memory device. The controller can perform at least one sub erase operation on each of the plurality of blocks, and variably increase an erase count of each of the plurality of blocks based on a timing of erasing data of each of the plurality of blocks through the sub erase operation.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10949113
    Abstract: Techniques for profiling storage blocks in non-transitory memory (e.g., flash memory dies) to determine their retention capability, and assigning them with labels based on retention, are described. A superblock (SB) can be formed from physical blocks with the same labels located in different dies. The disclosed system and methods improve storage efficiency when the update frequency of stored data is non-uniform, as is typically the case. Moreover, the disclosed embodiments improve the reliability of solid state drives (SSDs), as well as reduce data refresh frequency and write amplification due to periodic refresh. A storage system can comprise a controller configured to obtain expected retention times for a plurality of storage blocks. The controller can partition the blocks into superblocks based on the retention times. A respective superblock is associated with a superblock retention time range, and contains blocks having expected retention times within the retention time range.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Yu Cai, Naveen Kumar, Aman Bhatia, Fan Zhang
  • Patent number: 10949278
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for communicating error information during memory operations. For example, certain aspects of the present disclosure may provide a method for memory operations. The method generally including receiving a command from a host device, performing memory operations corresponding to the command received from the host device, detecting an error during the memory operations, and communicating the error based on the detection, wherein the error is communicated before receiving another command from the host device.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 16, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Asutosh Das, Vijay Viswanath, Ritesh Harjani, Srinivasan Karunelli
  • Patent number: 10937492
    Abstract: A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Norio Hattori
  • Patent number: 10923197
    Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: February 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Ashish Baraskar, Vinh Diep
  • Patent number: 10923195
    Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minkyung Bae, Tae Hun Kim, Myunghun Woo, Bongyong Lee, Doohee Hwang
  • Patent number: 10916309
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park