Abstract: A novel semiconductor device, a semiconductor device with low power consumption, or a semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first selection circuit connected to a plurality of first memory circuits, a second selection circuit connected to a plurality of second memory circuits, and a third selection circuit connected to a plurality of third memory circuits, thereby being capable of conducting power gating of each of the first memory circuits, each of the second memory circuits, or each of the third memory circuits separately. Accordingly, the memory circuits to which data is not written or from which data is not read can be kept in a state where power supply thereto is stopped, so that power consumption of the semiconductor device can be reduced.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

Abstract: A vehicle-mounted program writing device includes a plurality of vehicle-mounted control devices and a relay device. If a write start command button is turned on when a memory storage completion indicator is in an on state, the relay device starts the writing of the updated programs and the updated data to the vehicle-mounted control devices. If the memory storage completion indicator is in off state, the relay device does not execute the writing of the updated programs and the updated data even when the write start command button is turned on.

Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.

Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.

Abstract: A method of operating a storage device having a nonvolatile memory including at least one memory block having a plurality of sub-blocks includes reading backup data of backup memory cells having a highest program state among a plurality of memory cells connected to at least one word line of a sub-block which is not erase-requested adjacent to an erase-requested sub-block among the sub-blocks. The method includes storing the backup data, erasing the erase-requested sub-block, and reprogramming the backup memory cells having the highest program state on the basis of the backup data.

Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.

Abstract: A method, according to one embodiment, includes: receiving a recirculation command; performing a coarse page lookup to determine valid ones of logical pages to be recirculated; requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages; and sending write commands corresponding to verified valid logical pages from the fine page lookup. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Embodiments described herein are directed to systems and methods for ordering read sector data that has been returned from a hard disk controller out of order. For example, in typical storage systems, the firmware of the storage system and/or the host interface typically process read sectors in logical block address order. However, some of the data that is received may be received out of order. As such, the disk block hardware within the hard disk controller may accept these out of order sectors from the read channel and subsequently provide information that describes the available sectors that are in order to the firmware and/or the host interface.

Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Abstract: The wear of storage devices in a storage array or storage server cluster is unleveled via modal Read/Write to create a plurality of endurance sets, each endurance set having devices with statistically similar amount of wear in a given period of time, and different endurance sets are subjected to different amounts of wear over a given period of time. The storage devices are organized into RAID groups such that multiple devices associated with the same RAID group are not members of the same endurance set. The number of devices in each endurance set may be selected to match the number of spare failover storage devices.

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic.

Abstract: A system and method is disclosed for tracking block mapping overhead in a non-volatile memory. The system may include a non-volatile memory having multiple memory blocks and a processor configured to track a block level mapping overhead for closed blocks of the multiple memory blocks. The processor may be configured to track predetermined logical address ranges within which data written to a block fall, and then store the sum of the number of different logical address ranges for each respective block as a block address entropy metric. The method may include the processor using the block address entropy metric to select source blocks for garbage collection with a lower block address entropy metric or to adjust other operational characteristics such as data routing within the non-volatile memory system based on average block address entropy for a group of blocks.

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

Abstract: Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.

Abstract: A memory controller and methods thereof suitable for operating a system utilizing multiple memory bus channels and/or multiple banks of memory devices on each channel wherein the memory devices is polled only when necessary. The memory controller includes means for determining a status of each individual memory device of the plurality of memory devices, a channel controller for each memory bus channel, and at least one status register on which is stored a plurality of bits. The channel controller maintains a derived status of each individual memory device based on the current and previous status data. Each individual bit of the plurality of bits of the status register corresponds to an individual memory device of the plurality of memory devices and indicates the derived status of the individual memory device which are used to determine whether to check for a queued command destined for the individual memory device.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a read operation or a particular write operation may be performed on a correlated electron switch (CES) device by coupling a terminal of the CES device to a particular node through any one of multiple different resistive paths.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.

Abstract: Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.

Abstract: A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Abstract: A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found. The data erasing method and apparatus may be used in an implementation technology of the flash memory.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: A power-off period estimating method for a solid state storage device is provided. A memory array of a non-volatile memory of the solid state storage device includes plural blocks. Firstly, a first quality parameter of a first block of the plural blocks is calculated before the solid state storage device is powered off. When the first block is corrected at a first time counting value, a first read voltage set of the first block is acquired and the first time counting value is recorded. Then, the first block is corrected after the solid state storage device is powered on, so that a second read voltage set of the first block is acquired. Then, a power-off period is calculated according to the first quality parameter, the first read voltage set, the second read voltage set and the first time counting value.

Abstract: A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command.

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.

Abstract: Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a FIFO queue and searches can be subsequently generated for each search request. The resulting plurality of searches can be executed substantially in parallel on the database. A respective indication is transmitted to a requesting host when either each respective search is complete or each respective search has generated search results.

Abstract: Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for preventing overheating, for annealing non-volatile memory. An apparatus may include an array of non-volatile storage elements. A heating element may be configured to heat a first set of the non-volatile storage elements to anneal the first set of non-volatile storage elements. A heat shield or cooling element may be configured to prevent a second set of the non-volatile storage elements from overheating during annealing of the first set of non-volatile storage elements, to mitigate data errors for data stored on the second set of non-volatile storage elements.

Abstract: A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks.

Abstract: A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, generating a write address hash from the write address, making a first determination that a write history for a memory region includes the write address hash, and based on the first determination: clearing the write history, storing the write address hash in the write history, and making a second determination that a wear level operation is due, and based on the second determination: performing the wear level operation.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A memory controller circuit is disclosed. The memory controller circuit is coupled to an external memory device. The memory controller circuit selectively generates error-correction information for a user input. The selection is based on whether the user input is one of predefined inputs. In order to facilitate that, the memory controller circuit includes a command processor circuit and a memory circuit. The error-correction information is stored within the memory circuit located within the memory controller circuit. Selectively generating the error-free correction information may significantly reduce the amount of memory storage that is required within the memory controller circuit.

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract: Power transfer systems including a direct current source and a plurality of outputs operable in several modes. A ground mode may couple an output to circuit ground and a current mode may couple the output to the direct current source. The power transfer system may also include a controller configured to iteratively select a pair of outputs from the plurality of outputs. Once a pair is selected, the controller may set a first output of the pair of outputs to the current mode and the second to ground mode for a determined duration. After the duration has passed, the controller may set the first output to the ground mode and the second output to the current mode for the same duration. Thereafter the controller may select another pair of outputs.

Abstract: A memory circuit for storing a power failure event is presented. When a device restarts after a power supply failure, it usually resets its logic. This prevents the user from retrieving information relating to the power failure. The memory circuit comprises an input to receive a logic signal and an output to issue a logic value. The memory circuit also comprises a plurality of logic elements arranged such that upon powering the memory circuit, the output logic value has a greater probability of settling to a first logic value than a second logic value. Optionally, there is at least one memory element which comprises a first input and an output to issue a memory element logic value, wherein the memory element is operable between a first state in which the memory element logic value is zero and a second state in which the memory element logic value is one.

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.

Abstract: Technologies are generally described that relate to differential writing for life extension of portions of non-volatile memory that have a likelihood of error that satisfies a defined condition. An example method may include determining that at least two components of a memory device satisfy a defined condition; writing to a first component of the at least two components with first data having a first representation. The method may also include writing to a second component of the at least two components with second data having a second representation different from the first representation, wherein the second data comprises at least a portion that is bit inverted relative to the first data.

Abstract: Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.

Abstract: When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

Abstract: The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the predicted latency of the memory command.

Abstract: Systems and Methods are provided for increasing the number of writes to a page of non-volatile memory before the page must be erased. According to an embodiment, instead of writing a dataword directly to memory, a codeword is written to the memory location. The codeword is selected to minimize overwrite (e.g., bit-flipping) and to maximize the spread of wear across memory cells. In accordance with various embodiments of the invention, coset coding is integrated with error correction encoding; and once the previous state of a page is determined, a coset representative is selected on the basis of maximizing the number of writes to the page before erasing.

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.