Abstract: For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programmed during the prior programming operation.

Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Abstract: Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected memory blocks may include a first memory block that is to be programmed and a second memory block that is to be program-inhibited. The methods may also include applying a program voltage to a selected word line of the first memory block. The methods may further include applying a bipolar prohibition voltage to word lines of the second memory block.

Abstract: A method is provided for adjusting a read voltage in a flash memory device. The method includes storing first program count information when first pages of flash memory cells are programmed, the first program count information indicating a number of bits having a first logic value from among bits of data programmed in the first pages of the flash memory cells, and obtaining first read count information by counting a number of bits having the first logic value from among bits of data read from the first pages of the flash memory cells, while reading data from the flash memory cells using read voltages. The read voltages are adjusted based on the difference between the first read count information and the first program count information.

Abstract: In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.

Abstract: Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer.

Abstract: According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A flash storage system includes a data buffer configured to receive and store a data block having data portions. The system further includes flash storage devices having storage blocks interleaved among the flash storage devices and a controller coupled to the data buffer and the flash storage devices. The controller is configured to initiate data transfers for writing the data portions of the data block asynchronously into the storage blocks, where the data transfers for writing the data portions of the data block asynchronously into the storage blocks include reading the data portions of the data block from the data buffer serially and writing the data portions of the data block into the storage blocks in parallel.

Abstract: A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.

Abstract: Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge.

Abstract: A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract: Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.

Abstract: To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed.

Abstract: According to one embodiment, a memory system includes a memory that includes a plurality of parallel operation elements, each of which stores therein write data from a host device and on each of which read/write is individually performed, a control unit that performs the read/write to the parallel operation elements simultaneously, and a required-performance measuring unit that measures a required performance from the host device are included. The control unit changes the number of simultaneous executions of the read/write of the parallel operation elements based on the required performance measured by the required-performance measuring unit.

Abstract: According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.

Abstract: A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

Abstract: A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell.

Abstract: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.

Abstract: Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time.

Abstract: Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in the semiconductor substrate. The control unit, during an erase operation where electric charges written in the charge storage region are extracted to the channel region, periodically varies a voltage which is to be applied between the control gate and the channel region.

Abstract: A data processing method for a nonvolatile memory system is described. In the method, a host CPU calls N data file segments, generates logical addresses, and then transfers the N data file segments and logical addresses to an ASIC. The ASIC then maps the logical addresses onto physical addresses of a nonvolatile memory, derives N payload data segments, and collectively generates corresponding metadata for all of the N payload data segments. Then, a single multi-segment transfer operation is performed to sequentially write the N payload data segments to a data block in the nonvolatile memory, and thereafter, write the corresponding metadata to a metadata block associated with the data block.

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

Abstract: In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed has the correct value, regardless of the value in that state of any bit position that has not yet been programmed and is not being programmed. The programming of other bit positions based on subsequently arriving data should not then require a transition to an impermissible lower energy state. Although this may result in a transient condition in which some bits have the wrong value, by the time programming is complete, all bits would be expected to have the correct value. A cell may contain any number of bits equal to or greater than two, and programming may be performed cyclically (e.g., from LSB to MSB), anticyclically (e.g., from MSB to LSB), or in any random order.

Abstract: A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.

Abstract: A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract: In order to further develop a method of and a system (100) for controlling the programming of, in particular the erase/write access to, a memory device (10) comprising multiple memory cells (20, 22), said memory cells (20, 22) being exposed to wear resulting from repeated programming, in such way that an increased lifetime of the memory device (10), in particular on an integrated circuit, is provided even under exceptional stress of the memory device (10), it is proposed to provide—at least one quality measuring/determining means (40, 42) being assigned to each memory cell (20, 22) in order to measure and/or to determine the quality of the respective memory cell (20, 22), in particular in order to measure and/or to determine the prospective endurance specified according to a number of change cycles which the respective memory cell (20, 22) can endure within a performance tolerance, and—at least one control means (50), in particular by at least one access load distributor, —being coupled to each quality measur

Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

Abstract: A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.

Abstract: A lightweight radio/CD player for vehicular application is virtually “fastenerless” and includes a case and frontal interface formed of polymer based material that is molded to provide details to accept audio devices such as playback mechanisms (if desired) and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides EMC, RFI, BCI and ESD shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips. The PCB architecture is bifurcated into a first board carrying common circuit components in a surface mount configuration suitable for high volume production, and a second board carrying application specific circuit components in a wave soldered stick mount configuration.

Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.

Abstract: A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.

Abstract: A method and apparatus optimizes storage on solid-state memory devices. The system aggregates object storage write requests. The system determines whether objects associated with the object storage requests that have been aggregated fit in a block of the solid-state memory device within a defined tolerance. Upon the aggregation of object storage write requests that fit in a block of the solid-state memory device, the system writes the objects associated with the aggregated object storage write requests to the solid-state memory device.

Abstract: The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host.

Abstract: FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.

Abstract: Provided are a flash memory device and a method of verifying the same. The flash memory device includes: a memory cell for storing data; a sense amplifier for reading information of the memory cell; a load current input device for providing a load current to the sense amplifier; and a control circuit for controlling the load current input device to provide a load current during a memory cell reading operation, verifying the memory cell by using a program verify voltage if the memory cell is a programmed memory cell, and verifying the memory cell by using a compensated erase verify voltage if the memory cell is an erased memory cell.

Abstract: A program method, applied in a flash memory, includes the following steps. Firstly, a first memory sector and a second memory sector are selected, wherein the first and the second memory sectors respectively correspond to a first word line and a second word line. Next, a first operation phase and a second operation phase are determined. Then, the first word line is biased with a first setup voltage, and the second word line is driven in one of a program operation and a program-verification operation, in the first operation phase. After that, the second word line is biased with a second setup voltage, and the first word line is driven in the other one of the program operation and the program-verification operation in the second operation phase.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.

Abstract: A semiconductor memory device includes memory cell blocks having physical pages coupled to memory cells, peripheral circuits configured to program the memory cells or read data stored in the memory cells, and a controller configured to control the peripheral circuits so that a pre-program is performed to make memory cells in the memory cell blocks have threshold voltages higher than a set voltage by programming memory cells of the selected memory cell block, having threshold voltages lower than the set voltage, in response to an erase command. The set voltage is an intermediate threshold voltage obtained from the threshold voltages of the memory cells of the selected memory cell block.

Abstract: A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.

Abstract: When write request signal is input from a host device, an SSD inputs data input from the host device in an encoder sequentially and controls a RRAM to store data output from the encoder. When size of data stored in the RRAM reaches predetermined size Sref, the SSD controls the RRAM to read out data of size of the predetermined size Sref, inputs read data from the RRAM in the encoder, and controls a flash memory to store data output from the encoder. This configuration accomplishes the increase of the data write speed and improvement of reliability of the data.

Abstract: Systems and techniques for incrementally updating a software stack are described. The software stack can be stored on a flash memory device on a target device. A server computer can receive a modification to a function that is part of the software stack, wherein additional memory is allocated on the flash memory device to allow the function increase in size via a software update. Next, a new memory layout can be determined for storing functions in the software stack based on the modification to the function. The server computer can then determine changes to a set of memory pages on the flash memory device based on the new memory layout. Next, the server computer can send the changes to the set of memory pages to the target device.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.