Particular Read Circuit Patents (Class 365/189.15)
  • Memory with redundant sense amplifier
    Patent number: 8780650
    Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 15, 2014
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Michael E. Runas
  • Memory array
    Patent number: 8780624
    Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 15, 2014
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jing Gu, Bo Zhang, Weiran Kong, Jian Hu
  • Semiconductor device and data processing system
    Patent number: 8773919
    Abstract: In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miura, Satoru Hanzawa
  • Multilevel DRAM
    Patent number: 8773925
    Abstract: A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 8, 2014
    Assignee: Rambus Inc.
    Inventors: Yoshihito Koya, Brent Haukness
  • Read assist scheme for reducing read access time in a memory
    Patent number: 8773924
    Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Uddip Roy, Vinod Rachamadugu, Vamsi Krishna Grandhi, Setti Shanmukheswara Rao
  • Output driver circuit, output driver system and semiconductor memory device
    Patent number: 8767486
    Abstract: The output driver circuit includes a plurality of pull-up sub-drivers that pull up a voltage at the output terminal according to a pull-up signal based on the output data. The output driver circuit includes a plurality of pull-down sub-drivers that pull down the voltage at the output terminal according to a pull-down signal based on the output data. Selection from among the pull-up sub-drivers is made by an assigned pull-up calibration signal and selection from among the pull-down sub-drivers by an assigned pull-down calibration signal so as to make a pull-up current drivability and a pull-down current drivability for the voltage at the output terminal equal. A timing of turning on of the pull-up sub-drivers is calibrated by the pull-down calibration signal. A timing of turning on of the pull-down sub-drivers is calibrated by the pull-up calibration signal.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumiyoshi Matsuoka
  • Nonvolatile memory device capable of reducing read disturbance and read method thereof
    Patent number: 8767468
    Abstract: Provided are a nonvolatile memory device and a read method of the same. The read method applying one of a plurality of unselected read voltages to unselected wordlines adjacent to a selected word line. The voltage applied to the unselected word lines being based on which of a plurality of selected read voltages is applied to the selected wordline.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-il Lee, Moon Sone
  • Memory segment accessing in a memory device
    Patent number: 8767470
    Abstract: Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Systems and methods for auto-calibration of a storage memory controller
    Patent number: 8767471
    Abstract: Systems and methods for auto-calibrating a storage memory controller are disclosed. In some embodiments, the systems and methods may be realized as a method for auto-calibrating a storage memory controller including instructing a controllable delay circuit to delay a read strobe signal at one of a plurality of delay settings, receiving data captured at a data latch using the delayed read strobe signal, selecting an adjustment factor from the plurality of delay settings using a multi-scale approach, based on an accuracy of the data captured at the data latch, and instructing the controllable delay circuit to delay the read strobe signal by the adjustment factor.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: July 1, 2014
    Assignee: STEC, Inc.
    Inventor: Tsan L. Chen
  • NONVOLATILE MEMORY APPARATUS
    Publication number: 20140177355
    Abstract: A nonvolatile memory apparatus includes a read driver. The read driver unit is configured to apply read current to a memory cell in a normal read operation for outputting data stored in the memory cell, and apply refresh current larger than the read current to the memory cell in a refresh operation.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 26, 2014
    Applicant: SK HYNIX INC.
    Inventor: Dong Keun KIM
  • ZERO KEEPER CIRCUIT WITH FULL DESIGN-FOR-TEST COVERAGE
    Publication number: 20140177354
    Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: APPLE INC.
    Inventors: Hitesh K. Gupta, Greg M. Hess, Naveen Javarappa
  • Data transfer circuit and data transfer method
    Patent number: 8760941
    Abstract: A data transfer circuit includes a write circuit to control writing of write data to a memory, a read circuit to control reading of data from the memory, a first circuit to register a store position in the memory at which data written to the memory is stored, and a second circuit to store a data pattern when the write data is comprised of repeated patterns each identical to the data pattern, wherein the write circuit does not register the store position in the first circuit with respect to the written data that is comprised of the repeated patterns each identical to the data pattern stored in the second circuit, and the read circuit reads the data pattern from the second circuit for provision to a source issuing a read request when data requested by the read request corresponds to the data pattern stored in the second circuit.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventor: Masahiro Mishima
  • Semiconductor memory device with bit line charging circuit and control method thereof
    Patent number: 8760937
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, each of which is arranged at a position of between a word line and a bit line, a row decoder, and a bit line control circuit. And when data is to be read out from the memory cell, a charge control circuit controls the gate voltages of a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, so that the bit line is charged in accordance with a first characteristic obtained by increasing a current driving capacity of the first transistor during a desired period after start of charge of the bit line, and the bit line is then charged in accordance with a second characteristic obtained by returning the current driving capacity of the first transistor to the lower current driving capacity after elapse of the desired period.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Honda
  • Memory device and electronic device
    Patent number: 8760959
    Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Memory sensing using temperature compensated initial currents
    Patent number: 8760939
    Abstract: The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer E. Taylor, John D. Porter
  • Semiconductor memory device
    Patent number: 8755217
    Abstract: A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting circuit uses a function of generating precharge potentials to the pair of write bit lines based on data of the memory cell amplified by the data amplifier to set the precharge potentials of the non-selected pair of write bit lines to have a potential relationship corresponding to the data stored by the memory cell. As a result, data destruction of the non-selected memory cell during write operation is reduced or prevented, and the speed of operation is increased and the area is reduced.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Panasonic Corporation
    Inventor: Naoki Kuroda
  • Memory element and method for determining the data state of a memory element
    Patent number: 8750062
    Abstract: One embodiment of the present invention is directed to an electronic memory comprising a memory element and control logic that determines a data state of the memory element by: measuring a physical characteristic of the memory element to obtain a measured value corresponding to the data state, measuring the physical characteristic of the memory element, after setting the memory element to a first known data state, to obtain a first calibration value, comparing the measured value corresponding to the data state with the first calibration value to determine the data state; and determining a reliability metric for the determined data state.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: June 10, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gadiel Seroussi, Pascal Olivier Vontobel
  • Semiconductor chip and method for generating digital value using process variation
    Patent number: 8749265
    Abstract: Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to an first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 10, 2014
    Assignee: ICT Korea Co., Ltd.
    Inventors: Dong Kyue Kim, Byong-Doek Choi
  • Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device
    Patent number: 8750055
    Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Bum Kim, Hyung Gon Kim, Chul Ho Lee, Hong Seok Chang
  • Data input/output circuit and semiconductor memory device
    Patent number: 8750054
    Abstract: A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and generate a driving signal by amplifying data of a second input/output line coupled to a data input/output pad during a write operation; a read driving unit configured to drive the second input/output line in response to the data signal during the read operation; and a write driving unit configured to drive the first input/output line in response to the driving signal during the write operation.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Wook Kwack
  • Read Assist Scheme for Reducing Read Access Time in a Memory
    Publication number: 20140153346
    Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: LSI CORPORATION
    Inventors: Uddip Roy, Vinod Rachamadugu, Vamsi Krishna Grandhi, Setti Shanmukheswara Rao
  • Methods and systems for operating memory elements
    Patent number: 8743640
    Abstract: Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer Taylor, John D. Porter
  • Semiconductor storage device
    Patent number: 8743631
    Abstract: A semiconductor storage device includes a first cell array including a plurality of memory cells that are connected to a first word line and each of which is connected to each member of a first pair of bit lines. The semiconductor storage device also includes a second cell array including a plurality of memory cells that are connected to a second word line and each of which is connected to each member of a second pair of bit lines. The semiconductor storage device further includes a redundant cell array including a plurality of memory cells that are connected to a word line different from the first and the second word lines and each of which is connected to one member of the first pair of bit lines and to one member of the second pair of bit lines.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshiyuki Uetake
  • Bit line resistance compensation
    Patent number: 8743618
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: June 3, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • Current sense amplifier with replica bias scheme
    Patent number: 8743630
    Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: David Mueller, Thomas Nirschl
  • Method and circuit for testing a multi-chip package
    Patent number: 8743638
    Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: June 3, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Wen-Chiao Ho, Kuen-Long Chang
  • FAST MEMORY READ-OUT
    Publication number: 20140146622
    Abstract: Embodiments include systems and methods for faster memory read-out using a combined read-select circuit. A novel read-select circuit is described, which, when enabled for reading, concurrently reads its respective input line and selects its value for read-out by the circuit. This can reduce delays and unnecessary toggling resulting from separate read and select circuits. Some implementations also include a multi-global-line architecture that can reduce the number of read stages in the memory read-out circuitry, thereby further reducing read-out delays. Accordingly, embodiments can be faster and more efficient than many traditional implementations without relying on an increase in power consumption or clock speed.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jungyong Lee, Heechoul Park, Singrong Li
  • Memory architecture and design methodology with adaptive read
    Patent number: 8737144
    Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 27, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, ShaileshKumar Pathak, Kaushik Saha, Ashish Kumar, R Sai Krishna
  • SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME
    Publication number: 20140140148
    Abstract: A method of operating a semiconductor memory device includes performing a pre-read and a first main read to selected memory cells in response to a read request, and performing a second main read to the selected memory cells in response to a re-read request.
    Type: Application
    Filed: March 14, 2013
    Publication date: May 22, 2014
    Applicant: SK HYNIX INC.
    Inventor: Chi Wook AN
  • nvSRAM with inverted recall
    Patent number: 8724386
    Abstract: A RECALL process in a memory circuit includes RECALLing the state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kaveh Shakeri, Jay Ashokkumar
  • High capacity low cost multi-state magnetic memory
    Patent number: 8724413
    Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 13, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Mahmud Assar, Parviz Keshtbod
  • Display device integrated circuit (DDI) with adaptive memory control and adaptive memory control method for DDI
    Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Nonvolatile memory devices, memory systems and methods of performing read operations
    Patent number: 8717832
    Abstract: Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Bum Kim
  • Independently-controlled-gate SRAM
    Patent number: 8717807
    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 6, 2014
    Assignee: National Chiao Tung University
    Inventors: Ching-Te Chuang, Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Memory device and corresponding reading method
    Patent number: 8717825
    Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventor: Cesare Torti
  • Methods of quantizing signals using variable reference signals
    Patent number: 8717220
    Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • SRAM WITH IMPROVED WRITE OPERATION
    Publication number: 20140119100
    Abstract: A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array. Each memory cell of the array is coupled to a word line. The memory includes a row decoder that controls a voltage on each of the word lines and controls a voltage on each of the voltage supply lines. The row decoder provides a low voltage state voltage on one of the voltage supply lines during a write operation to a subset of memory cells coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Inventors: SAYEED A. BADRUDDUZA, Glenn C. Abeln
  • NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20140119139
    Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.
    Type: Application
    Filed: September 26, 2013
    Publication date: May 1, 2014
    Applicant: SAMSUNG ELECTONICS CO., LTD.
    Inventors: IL HAN PARK, SEUNG-BUM KIM
  • Semiconductor device and data processing system
    Patent number: 8711637
    Abstract: In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 29, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miura, Satoru Hanzawa
  • Non-volatile semiconductor memory and data processing method in non-volatile semiconductor memory
    Patent number: 8711604
    Abstract: A non-volatile semiconductor memory according to an embodiment includes: a data storage unit including a memory cell array and a writing circuit; an encoder that directs the writing circuit to write write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that decodes the read data into the information data.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Hideyuki Tabata
  • Using storage cells to perform computation
    Patent number: 8711638
    Abstract: A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 29, 2014
    Assignee: Zikbit Ltd.
    Inventors: Avidan Akerib, Oren Agam, Eli Ehrman, Moshe Meyassed
  • Memory controller and control method
    Patent number: 8705296
    Abstract: A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a second address of the memory after a write operation of the first dummy pattern by the first write circuit; a third write circuit configured to write a second dummy pattern including a plurality of consecutive second dummy values at a third address of the memory after a write operation of the first pattern by the second write circuit; a read circuit configured to read the written first pattern based on the second address of the memory; and a timing adjustment circuit configured to adjust a timing at which data is written into the memory based on a read first pattern.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventor: Shinya Aiso
  • Nonvolatile memory device and reading method thereof
    Patent number: 8705279
    Abstract: In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the operation of reading data.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 22, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se Hyun Kim
  • Sense amplifier scheme for low voltage SRAM and register files
    Patent number: 8705305
    Abstract: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bharath Upputuri
  • Semiconductor memory device, reading method thereof, and data storage device having the same
    Patent number: 8705276
    Abstract: A reading method of a semiconductor memory device having a multi-level memory cell includes the steps of: reading flag data indicating whether the most significant bit (MSB) of data programmed in the multi-level memory cell is programmed or not; storing the read flag data; reading the least significant bit (LSB) of the data programmed in the multi-level memory cell, based on the read flag data; and reading the MSB of the data programmed in the multi-level memory cell based on the stored flag data.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 22, 2014
    Assignee: SK Hynix Inc.
    Inventor: Wan Seob Lee
  • Semiconductor memory
    Patent number: 8705270
    Abstract: A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Takahashi, Yoshihiro Ueda
  • Semiconductor memory device and semiconductor system
    Patent number: 8699279
    Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Jin Kang
  • Obtaining soft information using a hard interface
    Patent number: 8693258
    Abstract: A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: April 8, 2014
    Assignee: Densbits Technologies Ltd.
    Inventors: Hanan Weingarten, Erez Sabbag
  • Method and apparatus for calibrating a read/write channel in a memory arrangement
    Patent number: 8693275
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 8, 2014
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Memory array with two-phase bit line precharge
    Patent number: 8693260
    Abstract: An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: April 8, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Yung-Feng Lin