Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

Abstract: A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).

Abstract: An apparatus and method of operating an open digit line and a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell, in one embodiment, has an area of 6F2. One method comprises, storing a first bit in a first memory cell and storing a second bit that is complementary to the first bit in a second memory cell. The first bit and the second bit form a data bit. The data bit is read by comparing a voltage difference between the first memory cell and the second memory cell.

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

Abstract: A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. The second transistor is coupled to a complement input of the storage element. The first wire selectively turns on the first and second transistors of one of the ports. The second wire provides the update value. The third transistor selectively couples the second transistor to ground depending upon whether the second wire turns on the third transistor, thereby providing a complement of the update value to the second transistor. The cell also includes one or more read ports for reading the storage element bit. A multi-ported register file may be created from the cells.

Abstract: The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: An isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode and as the other of the logic high and logic low during another portion of the standby power mode to prevent unnecessary switching every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. The switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is likewise prevented. In other embodiments, methods, electronic systems, wafers and DRAM are taught.

Abstract: A hierarchical bit line selection circuit is connected between a plurality of pairs of bit lines of a plurality of sub-arrays of a random access memory and a data line sense amplifier. The bit line selection circuit has a bit line selector circuit to selectively couple one pair of bit lines of the plurality of bit lines of each sub-array to the pair of local data lines. The bit line selection circuit further has a local data line selector circuit to select one of a plurality of pairs of local data lines to be connected to a pair main data lines that are connected to the inputs of the data line sense amplifier. The memory cell sub-arrays are folded in placement with the main data line switches to reduce data access time.

Abstract: Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A circuit, for controlling a write operation during which data from data lines is written to a memory cell, is used with a memory cell of the type that is connected to a row line and a first column line. An amplifier is connected across the first column line and a column line complimentary to the first column line. The column lines have a capacitance associated therewith. The circuit includes a control circuit for generating switching control signals. Switches are provided which are positioned in the column lines and are responsive to the switching control signals for selectively isolating at least a portion of the column lines during a predetermined portion of the write operation.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A memory array is divided into a plurality of memory blocks each having a plurality of bit line pairs. In the memory block selected for a data write operation, first and second selection gates are turned ON so as to couple first and second nodes to the power supply voltage and the ground voltage, respectively. In the data write operation, complementary bit lines of the same bit line pair are electrically coupled to each other through a bit-line coupling transistor. A bit-line current switching portion connects a plurality of bit line pairs in series between the first and second nodes so that the directions of reciprocating-current paths respectively formed in the plurality of bit line pairs correspond to the respective data levels of a plurality of bits.

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

Abstract: Sense amplifiers are alternately disposed on both sides of bit line pairs, switch circuits are provided so as to selectively connect two bit lines to a sense amplifier, and connection between a sense amplifier and a bit line is switched in accordance with an operation mode. Memory cells are disposed in rows and columns to satisfy the condition that the memory cells are arranged every other row in the same column. A low-power semiconductor memory device with improved access efficiency is provided due to selective activation of the sense amplifiers for reducing the number of the sense amplifiers activated at a time.

Abstract: A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an un-programmed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.

Abstract: Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.

Abstract: The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

Abstract: In the case that a refresh operation is carried out which is independent from an external access operation, both a data access method of a semiconductor memory device, and a semiconductor memory device are provided by which time suitable of each of these external access operation and refresh operation is set. While a time-measuring start signal “SIN” is entered into a path switching means, the path switching means is connected to either a first timer section or a second timer section under control of an external-access-operation-start-request signal REQ(O) and a refresh-operation-start-request signal REQ(I). Both the first and second timer sections measure both time “&tgr;O” and time “&tgr;I” to output a time-measuring stop signal “SOUT.

Abstract: A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).

Abstract: During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is used during the read operation to relay data from one part of the split bitline to the other. A weak pullup path is also provided to hold the non-driven end of the line in a stable condition. During non-read operations, the two sections of bitline are electrically connected.

Abstract: An SRAM array is disclosed. The SRAM array includes a plurality of SRAM cells. In one embodiment, the SRAM cells are 6-T SRAM cells that further includes a voltage bias device. The voltage bias device raises the voltage level of a low voltage rail Vss such that the plurality of SRAM cells are connected to a raised low voltage rail.

Abstract: Data of a plurality of memory cells are read on a plurality of first data lines and combined by a combination/rewrite circuit and transmitted on a second data line and the combined data is written back to the first data line. In combining data, the combination/rewrite circuit performs an addition. Mirrored data can be improved in reliability and a function of correcting an error of the mirror data can also be implemented.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: An apparatus and method of operating an open digit line and a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell, in one embodiment, has an area of 6F2. One method comprises, storing a first bit in a first memory cell and storing a second bit that is complementary to the first bit in a second memory cell. The first bit and the second bit form a data bit. The data bit is read by comparing a voltage difference between the first memory cell and the second memory cell.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

Abstract: Transistors (MN9, MN10) are connected in series between a node (N1) and a write data bit line (41), and have gates connected to a write control line (44) and a write word line (31), respectively. A potential corresponding to the exclusive OR of the write data bit line (41) and a write data complement bit line (42) is applied to the write control line (44). The write data bit line (41) and the write data complement bit line (42) which are not used for a write operation are precharged to the same potential to turn off the transistor (MN9). A memory device can reduce unwanted power consumption while rapidly performing a write operation which inverts a stored content.

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Abstract: An apparatus and method of operating an open digit line and a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell, in one embodiment, has an area of 6F2. One method comprises, storing a first bit in a first memory cell and storing a second bit that is complementary to the first bit in a second memory cell. The first bit and the second bit form a data bit. The data bit is read by comparing a voltage difference between the first memory cell and the second memory cell.

Abstract: In a multiple bits product, when respective bit is in a specific data direction, a selecting signal for making a corresponding column selecting switch ON is made ineffective. Thereby, in the multiple bits product, whether writing is executed in an arbitrary data direction can be selected for respective bit.

Abstract: A source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory dynamically controls cell transistor threshold voltage to increase cell stability, decrease cell standby power, and reduce cell delay. A memory cell includes a low storage node and a high storage node wherein the low storage node is driven below Vss during a read access and the high storage node is driven above Vdd during the read access.

Abstract: The present invention discloses a semiconductor memory device and a method of signal line arrangement. The semiconductor memory device comprises a plurality of memory cell array blocks, a number of pairs of local data input/output lines arranged along a longitudinal direction in each of the memory cell array blocks, multiple column selecting signal lines arranged along an orthogonal direction, and a number of twisted pairs of global data input/output lines arranged adjacent to and along the same direction as the column selecting signal line. Therefore, reducing signal coupling among the column selecting signal line and the pair of global data input/output lines.

Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of work lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines.

Abstract: A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.

Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell array divided into a plurality of sub-arrays in each of which a specified number of storage elements are arranged in the row direction, a first bit line provided for each of the plurality of sub-arrays and connected to one of a pair of storage nodes complementary to each other in the specified number of storage elements, a second bit line to which the first bit line provided for each of the plurality of sub-arrays is commonly connected via switching means, a third bit line commonly connected to the other one of a pair of storage nodes complementary to each other in the specified number of storage elements in the plurality of sub-arrays, and a write circuit connected to the second bit line and the third bit line.

Abstract: An apparatus includes a memory system having multiple memory subsystems that are operable to concurrently service memory transactions. The memory system has an interface arrangement with an interconnection network that allows for independent access to each memory subsystem, and logic blocks that support the servicing and distribution or routing of memory transactions. Preferably, the apparatus is formed on a semiconductor structure having a combination of compound semiconductor material and Group IV semiconductor material.

Abstract: In one aspect, reading a memory includes conductively coupling a memory cell and a first reference cell to respective lines of a selected bit line pair for a voltage development interval. During the interval a voltage differential develops on the bit line pair and is transmitted to a corresponding sense line pair. A second reference cell is precharged for the selected bit line pair for a reference cell precharging interval, the reference cell precharging interval being concurrent with at least a portion of the voltage development interval. A sense amplifier is enabled for a voltage detection interval. The bit line pair is precharged for a bit line precharging interval. The sense line pair is isolated from the bit line pair during the bit line precharging interval and the bit line precharging interval is concurrent with at least a portion of the voltage detection interval.

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

Abstract: A memory device having a plurality of data paths connected between a main memory by a plurality of data pads. Each of the data path transfers a first and second data bits from the main memory to a data pad in one clock cycle during a read operation. The first data bit is transferred to the data pad in a shorter path than the path of the second data bit.

Abstract: A method for preparing a computer memory cell for a data write operation thereto is disclosed. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices within the memory cell, and is connected at an opposite end to pull-down devices within the memory cell. The memory cell further has a pair of access transistors for selectively coupling the memory cell to a pair of complementary bitlines. In an exemplary embodiment, the method includes adjusting the voltage of the cell supply voltage source from a first voltage value to a second voltage value, the second voltage value being less than the first voltage value. The memory cell is then coupled to the pair of complementary bitlines, thereby facilitating the data write operation. Following the data write operation, the cell supply voltage is restored from the second voltage value back to the first voltage value.

Abstract: A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided, in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides of the sense amplifier array are connected to one another by wiring using the common electrodes.

Abstract: A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time.

Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

Abstract: Precharge circuits comprises PMOS transistors Q6 and Q7 each connected between a bit line and a power source potential VDD, PMOS transistors Q2, Q5, Q8 and Q11 connected between respective bit line pairs, and PMOS transistors Q21 and Q23 connected between respective adjacent bit lines of adjacent bit line pairs, wherein the gate electrodes of the PMOS transistors are each connected to a precharge control signal line PCG. The defect caused by omission of transistors from the prior art circuits is compensated by the PMOS transistors Q21 and Q23, each of which is required to be provided for two bit line pairs. With this and transistors of adjacent unit precharge circuits are arranged in plain symmetry, there is no need to provide transistors to be directly connected between bit lines *B2 and B3, and an average number of PMOS transistors for each bit line pair is less than 2.5.