Abstract: A semiconductor device includes memory cells, each of which is a dynamic storage device, a memory cell array where the memory cells in a predetermined number are arranged in a matrix, the memory cells being connected to intersections of orthogonal word lines and bit lines; first sense amplifying circuits for amplifying electric potentials of the bit lines; main bit lines arranged in parallel to the bit lines; a memory block array formed such that a plurality of memory blocks including switching circuits share the main bit lines, the switching circuits controlling conductivity between outputs of the first sense amplifying circuits and the main bit lines; first selecting means for selecting the word lines and the first sense amplifying circuits belonging to at least one memory block of the plurality of memory blocks; second selecting means for selecting the switching circuits belonging to one memory block of the plurality of memory blocks; a control signal generating circuit for controlling the second selecting

Abstract: A dynamic random access memory (DRAM) includes a Y-select circuit (218) that connects a pair of bit lines (204a and 204b) to a pair of sense nodes (210a and 210b). The Y-select circuit (218) provides a first impedance in a read operation, and a second impedance that is lower than the first impedance, in a write operation. Changes in Y-select circuit (218) impedance are achieved by driving transistors (N210a and N210b) within the Y-select circuit (218) with a first voltage during a read operation, and a second voltage during a write operation.

Abstract: A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch.

Abstract: The operating speed and stability of a semiconductor memory device of the type performing reading and writing at regular intervals are improved. A read/write pulse width controller varies the pulse width of a read/write pulse width control signal in such a manner that the width during reading is shorter than that during writing. A column decoder outputs a column-select signal having a pulse width equal to that of the read/write pulse width control signal. And a column-select gate connects an associated pair of bit lines to a pair of data lines while the column-select signal is high. During reading, a sufficiently long time can be allotted for equalizing potentials on the data lines. On the other hand, during writing, plenty of time can be allowed for connecting a pair of data lines to the pair of bit line. As a result, reading and writing can be performed stably enough at a sufficiently high speed.

Abstract: A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.

Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns and having a plurality of row lines, and a plurality of complementary digit lines. A plurality of sense amplifiers are included in the circuit, each sense amplifier sensing a voltage differential between first and second complementary digit lines and, in response to the sensed voltage differential, driving the first and second complementary digit lines to voltage levels corresponding to complementary logic states. A plurality of equilibration circuits are also included in the circuit, each operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibration signal.

Abstract: A memory device with skew-reducible memory cell arrangement, comprising a memory cell array being divided into a plurality of cell regions; a sense-amplifying means being comprised of a plurality of a first sense amplifiers disposed in the upper side of the memory cell and a plurality of second sense amplifiers disposed in the lower side of the memory cell array; a plurality of bit line pairs, each of bit line pairs being connected to the respective sense amplifiers and being divided into a plurality of bit line segment pairs; a connection means for connecting or disconnecting the bit line segment pairs to the sense amplifiers in accordance with a plurality of control signal pairs; and a control circuit for receiving a plurality of cell region selection signals for selecting corresponding one of the plurality of cell regions to generate the plurality of control signal pairs to the connection means.

Abstract: Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

Abstract: A self-timed data amplifier and method for an integrated circuit memory device which overcomes the power consumption problems of conventional static data amplifiers while providing a high speed amplification function within design margins. By self-timing the un-equilibration of the data lines ("DQ" and its complement "DQB"), powering the main data amplifier and latching its output all with the same clock that controls the column address for the device, a high speed, low power, low risk approach is achieved. In a particular embodiment of the present invention, this may be effectuated by the integration of an amplifying, latching and equilibration function wherein all of the related circuitry is controlled by the memory device Y-clock signal (YCLKB) and the write signal (WRITEB) signal. In operation, the YCLKB signal goes "low" when a column address is determined to be valid, which then allows the DQ and DQB lines to be driven.

Abstract: According to disclosed embodiments, a semiconductor memory (100) can include a restore voltage control circuit (106) that can supply a first internal voltage V.sub.INT that is lower than an external power supply voltage Vcc, a second internal voltage V.sub.INTS 1 that is lower than the first internal voltage V.sub.INT, and a third internal voltage V.sub.INT 2 equal to or less than the first internal voltage V.sub.INT and greater than the second internal voltage V.sub.INTS 1. The semiconductor memory (100) can further include a p-channel MOS transistor (T108) that can provide a conductive path between a voltage supply path (116) and a sense amplifier (104) in response to a sense signal Se at the first internal voltage V.sub.INT. A switch signal generating circuit (112) can supply a switch signal Sw that can change the potential on the voltage supply path (116) from the second internal voltage V.sub.INTS 1 to the third internal voltage V.sub.INTS 2 while transistor T108 is conductive.

Abstract: Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line.

Abstract: A memory device includes a plurality of bit lines, with each bit line serving at least one respective memory cell. A plurality of input/output lines are connected and parallel to the bit lines. The input/output lines allow data to be placed upon or extracted from the bit lines. Because the I/O lines are positioned parallel, rather than perpendicular, to the bit lines, the surface area required to implement the memory device does not increase in proportion to the number of bit lines provided. Accordingly, a relatively wide data path can be implemented on the memory device without significantly increasing the amount of surface area.

Abstract: There is disclosed an SRAM including a number of memory cells located in the form of a matrix. When data "0" is written to a memory cell 100, a precharge signal PC is brought to a high level so that a bit line D0 is brought into an electrically floating condition. A corresponding power switch 30 is turned off so that a pseudo-ground line SS0 is brought to an electrically floating condition. A corresponding equalizing transistor 20L is turned on so that the bit line having a power supply voltage Vdd as an initial potential and the pseudo-ground line SS0 having a ground voltage Vss as an initial potential are electrically connected to each other, so that the potential of the pseudo-ground line SS0 is elevated to a potential Veq which is determined by a ratio in capacitance of the bit line and the pseudo-ground line.

Abstract: A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In particular, a pair of WORD lines access the memory cell such that either WORD line being enabled provides access to the data in the memory cell. The memory cell contains two data storage cells. Each data storage cell contains a pair of cross-coupled transistors which are indirectly cross-coupled to each other via an isolation device. Further, each of the two data storage cells are cross-coupled to each other to reinforce and maintain the data in the respective cross-coupled data storage cell. In the event data is at risk in one of the data storage cells, the other storage cells maintains the data at the correct level at all times.

Abstract: In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

Abstract: In a DRAM semiconductor device comprising a bit line equalizer for setting a potential on paired bit lines to a potential on a precharge power source line, a sense amplifier circuit amplifying a potential difference across the paired bit lines and detecting data, sense amplifier drive lines, for applying a sense amplifier drive signal for driving the sense amplifier circuit to the sense amplifier circuit, and a sense amplifier/drive line equalizer, a current limiter element is so provided that, between a precharge power source line and the sense amplifier drive line, it is connected in series with the current path of the equalizer. By so providing the current limiter element, it is possible to, even if there occurs any cross-fail between the bit line and the word line, reduce a short-circuiting current at a precharging time or prevent generation of the short-circuiting current.

Abstract: A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.

Abstract: A method of operating a sense amplifier comprises floating an isolation gate line signal when a memory cell is being accessed. In one embodiment, the isolation gate is first turned on by biasing the gate line of the isolation gate. Then, the input of a sense amplifier is coupled to a desired memory cell and about the same time, the isolation gate is floated. The isolation gate is at least partially turned off by a reduction in the voltage level of the ISO gateline through capacitance based decay. This at least partially isolates other memory cells and/or circuitry accessed through a set of digit lines, allowing the sense amplifier to more easily sense the state of the desired memory cell. The isolation gate is floated by coupling the gate line of the isolation gate to a high impedance. The sense amplifier may be an N-sense amplifier. The isolation gate is floated prior to sense amplifier being activated.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells subdivided into array blocks each including M cell rows and N cell columns. The array blocks are arranged in array block rows and array block columns. Each cell of each cell row of each array block is coupled to an associated one of M word lines. Each cell of each cell column is selectively coupled to develop a data signal transmitted between an associated bit line pair including a primary bit line and a complementary bit line. A row decoder is coupled to provide a corresponding row address signal to each of the M word lines for addressing the cell rows.

Abstract: A static random access memory for improving the cell stability during read/write operation is provided. The SRAM comprises: a bit line and an inverted bit line; a memory cell coupled between the bit line and the inverted bit line for storing data; and a re-writing circuit coupled between the bit line and the inverted bit line for re-writing the data stored in the memory cell to the memory cell, in response to, at least, one read/write control signal for controlling read/write operation of the memory cell. The SRAM of this invention can be stably operated under low power voltage and/or at low temperature.

Abstract: The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.

Abstract: There is provided a dynamic type semiconductor memory device including (a) a first hierarchized complementary bit line, (b) a second hierarchized complementary bit line, (c) a first sense-amplifier electrically connected to the first bit line, (d) at least one second sense-amplifier electrically connected to both the first bit line and the second bit line, (e) a capacitor located between the first and second bit lines for each of second sense-amplifiers, and (f) a transfer gate arranged in series with the capacity between the first and second bit lines. The above-mentioned dynamic type semiconductor memory device makes it possible to store two-bit data in a single memory cell by employing a memory cell comprised of one transistor and one capacitor, without the use of a conventional memory cell having two transistors and one capacitor. Hence, the dynamic type semiconductor memory device ensures a significant reduction in a chip area.

Abstract: In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit.

Abstract: A semiconductor memory device in an SRAM using a 4 transistor-type memory cell which device includes an error writing protection circuit for preventing any information from being written into a memory cell into which any information is not needed to be written owing to line capacitance between adjacent bit lines. The error writing protection circuit includes an N-type transistors, a P-type transistor, and diodes. Hereby, it is determined whether or not a bit line is charged with electricity in accordance with electric potential of an adjacent bit line, and there is not charged with electricity a bit line for which there is no possibility of any information from being written, but there is charged with electricity only bit lines where there is possibility of any information being written in error. Thus, there is flowed no excess current.

Abstract: A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V.sub.CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the V.sub.CC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the V.sub.CC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the V.sub.CC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match sense line prior to a compare operation.

Abstract: A semiconductor memory has pairs of bit lines connected to its memory cells. Sense amps are connected across the bit line pairs. Column gate pairs are connected to the bit line pairs, and data bus pairs are connected to the bit line pairs via the column gate pairs. A column gate drive control circuit is connected to the column gate pairs and turns selected column gate pairs off during a write mask operation.

Abstract: Segment data line pairs connected to a bit line pair are separated into segment data line pair for reading, and segment data line pair for writing. Global data line pairs connected to segment data line pair are separated into global data line pair for reading and global data line pair for writing. Connection between bit line pair and segment data line pair for reading is provided through a first read amplifier, while segment data line pair for reading is connected to global data line pair for reading through a second read amplifier. The first read amplifier includes two MOS transistors connected in series between one of the segment data line pair for reading and the ground power supply, and two MOS transistors connected in series between the other one of the segment data line pair for reading and the ground power supply.

Abstract: The present invention concerns a memory structure wherein a plurality of memory cells such as SRAM are provided in columns and a plurality of bit line pairs are provided for each column. A write circuit drives a first bit line pair and writes data to the memory cells in the column; at the same time, a sense amp reads data by means of the second bit line pair. In that case, the first bit line pair and second bit line pair, provided in the same column, are driven with opposite phase signals. To prevent the reversal of the small potential difference of the second bit line pair for reading at that time, two bit lines, one bit line from the first and second bit line pairs, are arranged parallel in a first wiring layer and are interspersed with a fixed potential wiring. Furthermore, the two other bit lines from the first and second bit line pairs, are arranged parallel in a second wiring layer provided via an insulating layer and are interspersed with a fixed potential wiring.

Abstract: A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.

Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

Abstract: A circuit and operating technique acquires input write data available at the beginning of the first half cycle and passes the write data to read terminals, bypassing read data from a memory cell that is read during the first half cycle, while incurring no read access penalty. The circuit and operating technique bypass the input write data to the read terminal in place of data transferred from the memory cells. The data is forwarded to an node having a relatively large capacitance by connecting to the node very small devices with a small capacitance and with the small devices operating in saturation. The relatively large capacitance of the node is exploited to achieve a multiplexing functionality with effectively no delay.

Abstract: A precharge circuit is provided that produces a reference voltage that can be used for the precharge process, without a direct current flow from the supply voltage. In a preferred embodiment of this invention, the precharge circuit precharges one bus to the supply voltage, and the other bus to ground potential, then, while each bus is capacitively charged to each of the supply and ground potentials, the buses are connected together. Assuming substantially equal capacitance on each bus, the resultant voltage on each bus will be half the supply voltage. A charge transfer effects the precharging of the buses to the supply and ground potential; the only current drawn from the power source is the transient current associated with a switch of capacitive loads.

Abstract: An exemplary 18 MBit memory array includes four banks of array blocks. At the end of an active cycle, the exemplary memory array is automatically taken back into precharge without waiting for a control signal. One edge of a clock causes the memory array to execute a useful cycle, then to automatically reset itself in preparation for a new cycle, preferably using two sets of precharge signals- one is an automatically timed pulse, while the other stays on until the start of the next cycle. Both turn on automatically at the same time just after the selected word line is brought low. One equilibrate signal is turned off by a timed pulse just when the bit line equilibration is substantially complete (i.e., at the end of the active cycle), while the other equilibrate signal is turned off by the start of the subsequent cycle. The pulsed equilibrate signal drives much larger internal capacitive loads, such as large equilibration devices, while the non-pulsed (i.e.

Abstract: In a semiconductor memory circuit 100 according to the present invention, a column decoder 103 outputs column selecting signals to column lines (CL), whose output part is formed of inverter (125). A driving potential to be supplied to the inverter is set lower than a power supply potential Vcc supplied from outside. With this arrangement, a timing at which a bit line is connected to a data bus is determined by an amplification rate of a potential on the bit line, thereby providing the semiconductor memory device which performs a high speed and reliable operation.

Abstract: In a region of a transfer gate provided in a central portion of multilevel writing bit lines, noise in adjacent bit lines at the time of re-writing is counteracted by reversing the order of complementary bit line pair every other pair. With this, in a multilevel dynamic type semiconductor memory device in which one sense amplifier commonly includes a plurality of bit lines and some of the bit lines are selectively activated in a time-dividing manner, the influence of noise between the adjacent bit lines can be deleted.

Abstract: Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0.sub.n, D0.sub.n.sup..cndot., where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells.

Abstract: An SRAM comprises a memory cell array composed of a number of SRAM cells arranged in the form of a matrix, and a memory reading circuit including a sense amplifier for differentially amplifying a potential difference between a pair of complementary bit lines, for reading data from the memory cell array. The memory reading circuit includes a delay circuit for making the timing of a signal for deactivating a word line activating the SRAM cells on the same line and the timing of a signal for enabling the sense amplifier, consistent with each other. The delay circuit includes a number of cascade-connected inverters, and the number of the cascade-connected inverters can be adjusted by a focused ion beam. Thus, the reduction of the power consumption and the elevation of the reading speed, which are conventionally considered to be factors incompatible with each other, can be simultaneously realized by optimizing the number of the cascade-connected inverters in the delay circuit.

Abstract: An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit.

Abstract: A semiconductor memory includes a plurality of banks, a timing control circuits, and latch circuits. The timing control circuit is arranged commonly to the plurality of banks and outputs a signal for activating each bank and a signal for precharging each bank in a predetermined order at predetermined timings. Each latch circuit is arranged for each bank and latches the state of a signal output from the timing control circuit.

Abstract: A semiconductor memory is provided with a main amplifier circuit that is capable of selectively driving and precharging two I/O buses in conjunction with a write amplifier. The main amplifier circuit includes a separation and precharge section and an activation section. The activation section drives a signal for activating the first section to precharge the two I/O signals only when the two I/O buses are not being separated. The main amplifier circuit also includes both a main output bus and a test output bus. In so doing, the semiconductor memory can operate in a normal mode and a test mode. In the test mode, twice as many memory cells of the semiconductor memory can be accessed simultaneously, thereby reducing test time. The semiconductor memory, which can be one of many different data widths, has different sized output buses associated with each data width. Output buses with a relatively large capacitance can be produced with a large width, giving them a relatively small resistance.

Abstract: A circuit and method for limiting voltage swing on the complementary bit lines of a memory device. Complementary bit lines of the memory device are coupled to a sense amplifier through first and second p-channel isolation devices. A low voltage is applied to a gate of the p-channel isolation devices to activate the p-channel isolation devices such that one of the first and second p-channel isolation devices establishes the low logic level on one of the complementary bit lines at a voltage that limits the swing on the complementary bit lines.

Abstract: A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question.

Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires.

Abstract: A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit.

Abstract: When the data read out line is in the non-selective state, the data select line is at the "L" level, and therefore, the NMOS transistor is turned on, and to the data read out line, the capacity of the condenser is added. Therefore, the potential rising of the data read out line because of the influence of the coupling capacity just after the data select line has become at the "H" level, is small. After that, the memory cell data is transmitted to the data read out line, but at this time, the NMOS transistor becomes in the off state, and therefore, the capacity of the data read out line is reduced, so that the read out speed of the data may not be affected. Consequently, the signal interference because of the coupling capacity can be reduced.

Abstract: A circuit in a memory device for precharging at least one bit line before a data read operation of the memory device is complete. The circuit includes a sense amplifier having at least one input and at least one output. The bit line is connected to the input of the sense amplifier via column decode logic, and a precharge circuit is connected to the bit line. An input keeper is connected to the sense amplifier inputs and is in communication with the precharge circuit and column decode logic. The input keeper holds a content of the bit line at the sense amplifier inputs and causes the precharge circuit to precharge the bit line as the content of the bit line propagates to the output of the sense amplifier.

Abstract: A low power bank architecture implemented in memory access circuitry is disclosed. The bank architecture includes a bank circuit that has a bank core integrated with a pair of bitlines and a bank interface circuit that is coupled to the pair of bitlines. The bank architecture further includes a global data bus pair that is configured to communicate a less than full rail voltage swing. The global data bus pair is coupled to the bank interface circuit of the bank circuit that is designed to convert the less than full rail voltage swing into an up to about full rail voltage swing that is communicated to the pair of bitlines. The bank circuit is configured to be replicated once for each of the pair of bitlines in a memory core having an array of bank cores. By communicating memory access signals, such as differential write data, at a less than full rail voltage over the global data bus pair, a substantial amount of power is saved, which provides excellent power savings for many electronic device applications.

Abstract: An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by two adjacent cells. According to one embodiment, each memory cell includes a first transistor-based circuit in a first cell that is arranged to store information received over a corresponding one of the bit lines, and a second transistor-based circuit in a second cell that is arranged to output information over the same corresponding bit line.

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

Abstract: An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is supplied to the gates of the MOS transistors. A sense amplifier circuit is connected to the bit lines. The sense amplifier circuit amplifies the potential difference occurring between the bit lines, for the detection of data. The equalization control signal is output from a level conversion circuit. An internal boosted voltage-generating circuit constantly generates a boosted voltage which is higher than an externally-applied power supply voltage applied to a power supply terminal. The boosted voltage is applied to the level conversion circuit. The level conversion circuit converts an input control signal, whose high-level voltage is equal to, or lower than the externally-applied power supply voltage, into the boosted voltage, thereby generating the equalization control signal.