Abstract: A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.

Abstract: The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

Abstract: In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.

Abstract: The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

Abstract: A memory-cell array includes several memory cells arranged in rows and columns. The memory cells in each row include an access terminal coupled to an associated word line. The memory cells in each column are coupled between a respective first digit line and a respective complementary digit line. The complementary digit line is divided into several portions. A sense amplifier has first and second data terminals with the first data terminal coupled to the first digit line. The memory-cell array includes several first isolation devices, each first isolation device selectively coupling an associated portion of the complementary digit line to the second data terminal of the sense amplifier.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.

Abstract: Data of a plurality of memory cells are read on a plurality of first data lines and combined by a combination/rewrite circuit and transmitted on a second data line and the combined data is written back to the first data line. In combining data, the combination/rewrite circuit performs an addition. Mirrored data can be improved in reliability and a function of correcting an error of the mirror data can also be implemented.

Abstract: Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.

Abstract: A data input/output circuit for a semiconductor memory device includes a memory cell array, a latch-type sense amplifier for amplifying the cell data transmitted from the memory cell array in a read mode, a switching transistor for controlling a transmission of the cell data, and is connected between the memory cell array and the latch-type sense amplifier; and a write driver for storing an externally inputted cell data into the memory cell array in a write mode. The switching transistor separates the data line loading from the latch-type sense amplifier at a operation point of the latch-type sense amplifier, so that the operation speed of the sense amplifier is enhanced.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.

Abstract: A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires.

Abstract: A mechanism is provided for self timing a memory circuit to compensate for sense amplifier imbalance. The self timing mechanism comprises two self timed sense amplifiers. A first self timed sense amplifier reads a first state and a second self timed sense amplifier reads a second state. The control logic deactivates the real sense amplifiers in response to the slower of the two self timed sense amplifiers. Thus, even if there is a layout or processing variance, which causes the sense amplifiers to have a non-zero offset voltage and favor a certain output state when the inputs are equal, the real sense amplifiers are able to read the states of the memory cell.

Abstract: An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.

Abstract: A Flash memory sense amplifier precharge device having a self-bias circuit and a precharge circuit. The self-bias circuit is coupled to precharge a data node in response to a first control signal. The precharge circuit is coupled to precharge the data node in response to a second control signal, wherein the precharge circuit aids the self-bias circuit precharge the data node faster than the self-bias circuit could itself.

Abstract: A method and apparatus for sense amplification is disclosed. In one embodiment, this is a method of amplifying signals in a DRAM including sharing charge between a cell and a first conductor of a first pair of complementary conductors; and driving a voltage of the first conductor of the first pair and a voltage of a second conductor of the first pair in the same direction relative to a power supply voltage. In an alternate embodiment, this is an apparatus. The apparatus includes a first transistor having a first terminal, a second terminal and a gate. The apparatus also includes a second transistor having a first terminal, a second terminal and a gate, the gate of the second transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor coupled to the gate of the first transistor.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: A static random access memory (SRAM) device and a method for manufacturing the same are disclosed. In the SRAM device including a flip-flop circuit including two access transistors and a pair of inverters, connection lines for connecting the inputs and outputs of the inverters, and a word line, power supply lines and bit lines are formed of a metal interconnection. The resistance of interconnection can be reduced and the SRAM device manufacturing process can be performed along with CMOS standard logic manufacturing process.

Abstract: A local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal to couple complimentary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.

Abstract: In the configuration of a charge confinement type sense amplifier, activation/inactivation of a charge containing gate and activation/inactivation of a sense amplifier circuit are controlled by different control signals. Thus, a layout area of the sense amplifier for reading of internal data is reduced.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline.

Abstract: In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.

Abstract: A semiconductor memory device includes two power feed lines. An overdriving scheme is applied to one of the power feed lines in the sensing amplifying operation, and no overdriving scheme is applied to the other power feed line in the sensing operation. According to the overdriving scheme, the power feed line is overdriven to a potential level higher than a potential corresponding high level data stored in a memory cell. Thus, the overdriving of the power feed line is applied as an auxiliary function to prevent application of an excess potential to a memory cell capacitor. Such a semiconductor memory device can be achieved that improves both the speed of sensing amplifying operation and the reliability of memory cell capacitors, while conforming to low voltage operation requirement.

Abstract: Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.

Abstract: There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . .

Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second a invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.

Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states.

Abstract: Disclosed herein is a sense amplifier circuit which includes a first, a second and a third similar load transistors. The first and second load transistors supply a dummy data line with a current of the same amount to one another. Acting in a current mirror configuration, the third load transistor supplies a data line with a current equaling the total current supplied by the first and second load transistors. A dummy memory cell is composed of the same transistor as an on-state memory cell. According to this sense amplifier structure, it is very easy to obtain a dummy cell current which has an intermediate value consistently between an on cell current and an off cell current of the memory cell, which are supplied from the third load transistor to the data line. The improved intermediate value yields a reliable readout of the memory cell.

Abstract: Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

Abstract: An output circuit is driven by a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.

Abstract: A ternary dynamic CAM cell compatible with a standard logic process includes two ratio-independent 4-transistor (4T) SRAM cells. Each 4T SRAM cell includes a pair of cross-coupled driver transistors for storing data value, and a pair of access transistors. The driver transistors are sized to not be stronger than the access transistors. In one embodiment, the driver and access transistors are PMOS and NMOS, respectively, and are all substantially the same size. A match circuit for each 4T SRAM cell includes a pair of pass transistors serially coupled between a match line and a supply voltage. If the comparand and stored data bits do not match, both pass transistors are turned on, pulling the match line to the supply voltage. “A DON'T CARE” state is created by writing the same logic value to both 4T SRAM cells, so that both match circuits remain off for all input comparands.

Abstract: Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

Abstract: In the present invention a bit line precharge circuit is used to prevent errors from a write operation in memory cells adjacent to the column being written. The precharge circuits are enabled by write enable and selected by the Y decoder in such a way that only precharge circuits on bit lines adjacent to the active bit lines in a write operation are activated. All other precharge circuits on bit lines more remote than immediately adjacent bit lines are not activated and thus saving power during a write operation.

Abstract: A pair of coupling transistors are connected in series with isolation transistors in each of a plurality of column node circuits coupled to first and second arrays of memory cells arranged in rows and columns. The coupling transistors for the complimentary digit lines in each column node circuit are rendered non-conductive in the event memory cells connected to the coupling transistors through digit lines of the first and second array are defective. As a result, defective memory cells in the first and second arrays are isolated from sense amplifiers in the column node circuits so that the sense amplifiers cannot affect non-defective memory cells.

Abstract: A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where “Sel” is a cell selection signal representative of the address, “W” is a write command, {overscore (W)} is a read command, “D” is the data to be written into the addressed cell and “.” indicates the AND function.

Abstract: A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.

Abstract: A semiconductor memory device for providing data together with an echo clock as an indicating signal representing a time for providing or presenting data in an electronic system is described. The device comprises an echo data latch circuit for generating a source signal of the echo clock in response to an output of a sense amplifier for sensing and amplifying the data of a memory cell during a read operation, and for producing the source signal of the echo clock in response to a predetermined level of power voltage during a write operation; and an output circuit, connected between the echo data latch circuit and an echo clock output terminal, for receiving the source signal of the echo clock and for outputting the echo clock to the output terminal in response to control data relating to an external clock, thereby minimizing or reducing clock skew and also preventing speed push.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.