Abstract: A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.

Abstract: An apparatus for pre fetching and restoring data stored in memory cells in a semiconductor memory device includes a bit line sense amplifying unit and a control unit. The bit line sense amplifying unit senses the data stored in the memory cells in response to a bit line sense amplifier driving signal. The control unit drives the bit line sense amplifying unit before data applied on pairs of bit lines are transferred to pairs of data bus lines in response to a control signal during a pre fetching operation. Additionally, the control unit drives the bit line sense amplifying unit after data applied on the pairs of bit lines via the pairs of data bus lines is transferred to the pairs of bit lines in response to the control signal.

Abstract: The semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit; a data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to main memory unit. By means of the present invention, it is possible to efficiently conduct data transfer between a main memory unit and an auxiliary memory unit having different operational voltages, and moreover, it is possible to effectively suppress interior noise which is generated.

Abstract: Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A write control circuit of a DRAM core cell includes a sense amplifier and first to third N channel MOS transistors. The first and third MOS transistors constitute a column selection gate. If data “1” is written, a write mask signal and a data line are set at L level to render the second MOS transistor nonconductive. If data “0” is written, the write mask signal and the data line are set respectively at L and H levels to render the second MOS transistor conductive. In order to inhibit data rewriting, the write mask signal and the data line are both set at H level to render the second and third transistors nonconductive. Layout area and power consumption can be reduced compared with the conventional approach which requires two data lines.

Abstract: The present invention provides a circuitry for supplying data from a write input/output line pair to a digit line pair for writing the data into memory cells. The circuitry comprises: a balancing device for balancing in voltage level between the write input/output line pair by making a connection of the write input/output line pair; and a controller connected to the balancing device for controlling balancing operations of the balancing device.

Abstract: A semiconductor memory includes a control signal generator for generating a first control signal, a second control signal, and a third control signal; a first inverter for receiving an external address in accordance with the first control signal; a latch enabled by the second control signal and latching an output of the first inverter; and an address signal generator enabled by the third control signal, the address signal generator generating complementary address signals by using outputs of the first inverter and the latch.

Abstract: In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.

Abstract: A precharge circuit for a memory device includes a first precharge sub-circuit that precharges data input/output lines to a first level for a write operation, and a second precharge sub-circuit that precharges the data input/output lines to a second level higher than the first level for a read operation. Therefore, even when a power supply voltage of the semiconductor memory is low, the input/output lines are precharged to a sufficiently high voltage and an input/output sense amplifier can operate normally, thereby outputting correct data.

Abstract: A K way cache memory having improved operational speed and reduced power consumption is provided. The cache memory includes M cache memory units, but only activates one of the units at a given time. Moreover, only one match line is activated corresponding to a way having a tag address that matches an externally provided tag address.

Abstract: A semiconductor memory with static memory cells has an n-well in which pMOS transistors are formed and a p-well in which nMOS transistors are formed. The n- and p-wells are divided into blocks each containing a given number of memory cells. The n- and p-wells in each block receive voltages that vary depending on whether or not the memory cells are selected. If the memory cells are selected to operate, the threshold voltage of each transistor in the memory cells is decreased to increase current to be taken out of the memory cells. If the memory cells are not selected, the threshold voltage is increased to reduce leakage current of the memory cells. This arrangement suppresses standby current and improves the operation speed of the memory cells.

Abstract: A semiconductor memory device having input/output sense amplifiers capable of varying gains using a column address and block selection signals. The input/output sense amplifiers can compensate for reduction of transfer rate according to distance between a selected memory block or sub memory block and the sense amplifiers. A semiconductor memory device of the present invention includes: a plurality of sub memory blocks divided by a column address in a memory block; a plurality of data input/output line pairs coupled to the sub memory blocks, for transmitting data in a selected sub memory block; and a plurality of input/output sense amplifiers for sensing and amplifying data from the data input/output line pairs, wherein each of the input/output sense amplifiers has a variable gain characteristic depending on distance between the selected sub memory block and the input/output sense amplifiers so as to minimize a difference in delay characteristic according to position of the selected sub memory block.

Abstract: Rapid data transfer and reduction in power consumption can be achieved by reducing the number of row accesses. A pattern of the memory regions to be selected in memory array is changed by word line mode designation of word line mode control circuit. Memory cells in the same row are selected in a line mode, whereas memory cells in different rows are simultaneously selected in a box mode.

Abstract: A semiconductor device includes a plurality of bitlines arranged in an array, the plurality of bitlines being grouped in pairs and at least some of the bitlines include a twist. A twist region is disposed along the plurality of bitlines wherein the twist region occupies layout area designated for the twists. An equalizer element is disposed in the twist region for equalizing a pair of bitlines.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: The circuit generally comprises a bit line, a complementary bit line, a memory cell and a read circuit. The memory cell may be configured to (i) discharge the bit line in response to a memory sense period and (ii) charge the complementary bit line in response to said memory sense period. The read circuit may be configured to (i) precharge the bit line prior to the memory sense period, (ii) discharge the complementary bit line prior to the memory sense period, and (iii) detect when the bit line and the complementary bit line achieve a predetermined voltage separation in response to the memory sense period. The circuit may be used in asynchronous memories.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: The integrated memory has memory cells each with two transistors and two capacitors. Unlike conventional 2-transistor/2-capacitor memory cells, the plate electrodes of the capacitors are connected to different plate potentials.

Abstract: According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.

Abstract: A semiconductor integrated circuit comprising a memory cell, a column switch for transmitting data to a bit line, a sense amplifier for amplifying data, a precharging circuit for charging the bit line, and a control unit. The control unit controls the transfer switch in the memory cell, the column switch, the sense amplifier, and the precharging circuit so as to differentiate the control timings of these circuits between a write operation and a read operation. For example, the column switch is turned on after the transfer switch is turned on and before the amplification of the sense amplifier is started in a write operation. Here, the data retained in the memory cell are rewritten into write data before amplified by the sense amplifier. This minimizes the data inversion time and heightens the speed of write operations. The power consumption can be reduced since the circuits optimally operate in accordance with the operating modes.

Abstract: A semiconductor memory device includes: a global I/O line pair having a global I/O line and a complementary global I/O line; a data I/O buffer unit, coupled to the global I/O line pair; a plurality of banks, coupled to the global I/O line pair, for storing data, said banks including: a first bank coupled to the global I/O line pair; and a second bank coupled to the global I/O line pair, wherein the second bank is located closer to the data I/O buffer unit than the first bank is; a control signal generating unit for generating a control signal, said control signal has a first level and a second level in a read operation and a write operation, respectively; a first precharge unit located closely to said first bank, said first precharge unit sensing a level transition of the global I/O line pair and precharging the global I/O line pair in response to the control signal of the second level in a write operation; and a second precharge unit located closely to said second bank, said second precharge unit sensing a l

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: Bit line capacitance variation devices are respectively connected to the bit lines contained in a ferroelectric memory device. These bit line capacitance variation devices change the capacitance of bit lines according to the bit line potential during operations for reading data from the ferroelectric memory device.

Abstract: A modified binary content addressable memory (CAM) (700) having a fast variable prefix matching capability is disclosed. The modified CAM (700) includes modified CAM cells (702(0,0) to 702(n,m)), each of which includes a store/compare circuit (704(0,0) to 704(n,m)) for storing a data value and comparing the data value to a comparand value. In addition, each modified CAM cell (702(0,0) to 702(n,m)) further includes a multiplexer (MUX) circuit (706(0,0) to 706(n,m)). Each MUX circuit (706(0,0) to 706(n,m)) receives a non-shifted comparand value from a modified CAM cell of a previous row and same column, and a shifted comparand value from a modified CAM cell of the previous row and an adjacent column. The MUX circuits (706(0,0) to 706(n,m)) enable a comparand value to be shifted as it is applied to consecutive data values.

Abstract: A semiconductor storage device capable of detecting a high resistance shortcircuit between a storage node of a memory cell and a gate in a transistor of the memory cell. A sense amplifier activating signal generating circuit section 13 in a ROW control section 2 delays, by a predetermined time, a timing for activating sense amplifier activating signals SON and ZSOP in a test mode in which a High-level test mode signal TM is input, delays, by a predetermined time, a timing for activating each of the sense amplifiers of the sense amplifier section 3, and detects a high resistance shortcircuit caused between a storage node SN in the memory cell and a gate TG of the transistor.

Abstract: Resistance of a memory cell element in a resistive cross point memory cell array is sensed by a read circuit including a differential amplifier, a first direct injection preamplifier and a second direct injection preamplifier. During a read operation, the first direct injection preamplifier is coupled to a first input node of the differential amplifier, and the second direct injection preamplifier is coupled to a second input node of the differential amplifier.

Abstract: A reduced line select decoder for a memory array provided comprising a plurality of memory cells arranged at least in one column, a bit line pair connected to the memory cells arranged in one column, a sense amplifier coupled to a bit line pair for differentially amplifying the voltages on the bit line pair in accordance with the voltage on the sense drive line, and a sense amplifier control input responsive to activation of a sense instructing signal to latch data into the sense amplifier and a pair of read/write control signals to select and provide a read/write operation to a selected bit line and connecting to write buffer.

Abstract: A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first circuit at the one or more predetermined times. A third circuit logically inverts data to be written to and data read from the ferroelectric memory device following every other predetermined time. In this way, the circuit is capable of inverting the data values stored in the ferroelectric memory device, thereby reducing the susceptibility of imprint.

Abstract: A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires.

Abstract: Where the same data is stored for an extended period of time, the possibility exists of unwanted burning in of the data which would allow undesired recovery of erased data even after it has been over-written or the memory has been powered down. The memory contents are therefore periodically rewritten in the inverse of their former state, either to the same location in which they were previously stored, or elsewhere. Inversion may be performed in an invert cycle during which address decoders driven by a high speed oscillator read each cell and write back its contents inverted. On completion of a cycle, a latch may indicate whether the stored data is in a true or complement form. The latch may control programmable invertors so that cells are always read or written correctly, regardless of whether data happens to be in true or complement form.

Abstract: A spare memory array having spare memory cells common to a plurality of normal sub-arrays having a plurality of normal memory cells is provided. A spare line in the spare array can replace a defective line in the plurality of normal sub-array. The defective line is efficiently repaired by replacement in an array divided into blocks or sub-arrays.

Abstract: Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines: after signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, as fed with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned from the intermediate potential level to the select level in response to the selecting operation of the column select circuit.

Abstract: A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

Abstract: In a dynamic random access memory (DRAM) being operated at a low power-supply voltage, a bit line sense-amplifier for amplifying the electric charge first amplifies a cell charge applied to a bit line with a sufficient potential difference, prior to sensing the cell charge in a bit line sense-amplifier, thereby stably and quickly performing a sensing operation.

Abstract: Only one sense signal line for driving a sense amplifier is arranged in each sense amplifier band. Each sub-array is provided with a sub-sense signal generator for generating two sub-sense signals in response to a main sense signal sent from one main sense signal line. The sub-sense signal is applied to the plurality of sense amplifiers corresponding to each sub-array. Since only one main sense signal line is arranged in each sense amplifier, a layout area is reduced. Preferably, a transistor of a first inverter in the sub-sense signal generator is smaller in size than a transistor of a final inverter. Thereby, a significant delay of the sub-sense signal does not occur in a position remote from a source of the main sense signal.

Abstract: The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.

Abstract: Switch MOSFETS are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, supplied with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier.

Abstract: Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0n, D0n*, where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells.

Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. In an exemplary embodiment during an internal write operation, write circuitry supplies a small differential voltage to the selected bit line sense amplifiers, which “swallows” the normal read signal, before bit line sensing. The bit line sense amplifiers then “write” the level into the memory cell during normal latching. This provides for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by letting a selected bit line sense amplifier restore the voltage levels onto the selected bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell.

Abstract: A CMOS memory array, including a number of bit cells arranged in an array of N rows and M columns includes a duplicate column of bit cells that is used for self-timing. Receipt of an address will access a predetermined number of the bit cells to generate a reset signal that is used to enable sense amplifiers for sampling bit lines of the array.

Abstract: A semiconductor memory device includes a pair of data lines, a precharging and equalizing circuit, a setting circuit and a data write circuit. The precharging and equalizing circuit is provided between the data lines to equally precharge the data lines to a first voltage in response to a precharge and equalize signal. The setting circuit is provided between the data lines to set one of the precharged data lines to a second voltage in response to data signals. The second voltage is lower than the first voltage. Also, a data Is written to a memory cell based on the second voltage of the one precharged data line and the first voltage of the other precharged data line. The data write circuit supplies the data signals to the setting circuit based on the data.

Abstract: A semiconductor memory device precharges IO lines of the device rapidly at a write interrupt in normal and full page modes. The device includes a write interrupt detector, a precharge signal generator, and a precharge circuit. The write interrupt detector detects whether signals indicating a write interrupt in the normal mode are from the outside, and then generates a write interrupt detection signal. The precharge signal generator generates first and second precharge signals in response to the write interrupt detection signal, and the precharge circuit precharges IO lines at both sides of a memory cell array of the device before a read or write operation in the normal mode in response to the first and second precharge signals. Since the address access time of the semiconductor memory device is short, a high-speed semiconductor memory device can be implemented using the present invention.

Abstract: A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared between two pairs of bit lines. Half of the bit line pairs within each array block are served by a sense amplifier located above the array block, and the remaining half are served by a sense amplifier located below the array block. A read amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a bus line before bit line sensing has occurred. This read amplifier may be connected to the bit lines, the internal sense amplifier nodes, a local I/O line, or a local output line. In a preferred embodiment, a second stage amplifier further buffers the signal and drives a pair of global output lines which extend the full height of the memory bank to respective I/O circuits.

Abstract: The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

Abstract: In semiconductor memories, memory banks are activated via memory bank decoders. The memory bank decoders assigned to different groups of memory banks have a layout that is symmetrical with respect to an axis of mirror symmetry. A changeover is made between the memory bank decoders by a predecoder. For this purpose, the predecoder generates enable and address signals for the memory banks. This enables the memory bank decoders to be disposed on the semiconductor chip in direct proximity to the respectively assigned memory banks.

Abstract: An integrated memory has memory cells disposed in a cell array at crossover points of bit lines and word lines for storing information items. In addition, the memory has a word line decoder by which the word lines can be addressed, and at least one evaluation unit for evaluating the information items read from the memory cells onto the bit lines and the evaluation unit has an activation input. In addition, the integrated memory has a logic unit for performing an OR function and has inputs connected to that end of each of the word lines which is remote from the word line decoder. The logic unit further has an output connected to the activation input of the evaluation unit. The logic unit serves for time-optimized activation of the evaluation unit as soon as one of the word lines has been selected by the word line decoder.

Abstract: A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.