Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: In a memory cell, the cell ratio between an N-channel MOS transistor as a driver transistor and an N-channel MOS transistor as an access transistor is 1. To the first and second storage nodes, capacitors are connected, respectively. A word line driver receives a voltage obtained by boosting a power source voltage from a boosted power source voltage generating circuit and activates a word line with the boosted voltage. A bit line precharge circuit precharges bit lines to the power source potential when the word line is inactivated in accordance with a signal outputted from a BLPC signal generating circuit.

Abstract: A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements, which are clocked by a common clock line and loaded from a common data input line. A common reset line may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate, such as a NAND gate, receives the storage element outputs and flags improper loading of data. Inverters on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.

Abstract: A method and circuit increases the capacitance of a digit line coupled to a memory cell capacitor during a memory read operation. The increased capacitance on the active digit line coupled to the memory cell capacitor causes it to respond slower to activation of a negative sense amplifier than a reference digit line that is also coupled to the sense amplifier. As a result, the sense amplifier favors sensing a high voltage from the memory cell thereby decreasing the required refresh rate of the memory cells because memory cell capacitors storing a high voltage tend to discharge faster than memory cell capacitors storing a low voltage.

Abstract: A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Abstract: A semiconductor memory device uses memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability. A semiconductor memory device includes memory cells formed on a main surface of a semiconductor substrate, and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor; and bit and word lines for controlling an operation of the memory cells, a cell plate forming an electrode of the capacitor being formed of the same layer as the gate electrode.

Abstract: According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Abstract: A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements, which are clocked by a common clock line and loaded from a common data input line. A common reset line may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate, such as a NAND gate, receives the storage element outputs and flags improper loading of data. Inverters on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: There is disclosed a memory system including a memory cell array, a sense amplifier circuit, a write circuit, a level setting circuit, a column decoder, a data line, and a sense amplifier control circuit. The level setting circuit sets external input data to substantially the same level as a read potential difference level from the memory cell. The external input data whose level has been set by the level setting circuit is transferred to the sense amplifier selected by the column decoder via the data line. The sense amplifier control circuit activates the selected sense amplifier so as to write the external input data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.

Abstract: A memory device having single event upset (SEU) resistant circuitry includes a first inverter having an input and an output, a second inverter having an input and an output, a first transistor having a gate coupled to the input of the first inverter and having source and drain regions coupled to the output of the second inverter, and a second transistor having a gate coupled to the input of the second inverter and having source and drain regions coupled to the output of the first inverter.

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM), cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Abstract: A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or associated resistance of the transistors within the sense amplifier.

Abstract: An MRAM comprises a plurality of magnetic memory cells, a plurality of local word lines, each of the local word lines being operatively coupled to at least one memory cell for assisting in writing a logical state of the at least one memory cell corresponding thereto, a plurality of global word lines, each of the plurality of global word lines being connected to at least one of the plurality of local word lines, the global word lines being substantially isolated from the memory cells, a plurality of write circuits operatively coupled to the global word lines, and a plurality bit lines operatively coupled to the memory cells for selectively writing a logical state of one or more of the memory cells. Each of the write circuits is configurable as a current source and/or a current sink for supplying and/or returning, respectively, at least a portion of a write current for assisting in writing one or more memory cells.

Abstract: An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

Abstract: To provide a data holding device and a data holding method with which data can be held even when the power source is interrupted and the held data can be restored accurately, which does not largely increase the circuit area, and which does not require fine timing control. In data restoring operation, a reading signal is applied to the other end 5b of a ferroelectric capacitor 5 with the power source of the data holding device 1 on. An electric charge corresponding to a polarization state stored in the ferroelectric capacitor 5 is thereby discharged to a ferroelectric connecting node 17. At this time, transfer gates 11 and 15 are both off. Thus, the electric charge discharged to the ferroelectric connecting node 17 does not leak through the transfer gates 11 and 15. The potential at the ferroelectric connecting node 17 accurately reflects the discharged electric charge.

Abstract: A control circuit for a memory array device having one or more memory storage cells associated therewith includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a wordline associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.

Abstract: A memory circuit 2 includes a plurality of memory cells 4, 6 which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit lines A, Abar, B, Bbar associated with the memory cells 4, 6. During a subsequent precharge operation serving to restore the precharged voltage levels of the bit lines A, Abar, B Bbar charge sharing is performed between non-accessed bit lines and those which have been accessed and accordingly at least partially discharged. Also the precharging circuits 12, 14, 16, 18 associated with the non-accessed bit lines contribute towards the precharging operation.

Abstract: A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Abstract: A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.

Abstract: A memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and at least one bit line, in which at least two word lines are associated with each row, and at least two adjacent columns share at least one same bit line, two memory cells of the two adjacent columns belonging to a same row being connected to different word lines.

Abstract: The present invention discloses a standby current reduction circuit applied in DRAM, which comprises a pre-charge circuit and a current-limiting means. The pre-charge circuit provides a pre-charge current to the pair of complementary bit lines of DRAM only in the operating mode. The current-limiting means provides only a small pre-charge current to the pair of complementary bit lines of DRAM. With the pre-charge current provided by the pre-charge circuit, it can reduce the pre-charge current required by the current-limiting means to supply, and further reduce the leakage current forming in the standby mode due to short circuit between the pair of complementary bit lines and the word line of DRAM.

Abstract: An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).

Abstract: A semiconductor memory which operates at low power supply voltage with lower power consumption without decreasing writes rate is provided. During data read, a virtual ground line VGj provided to correspond to a bit line pair BLj, /BLj of a read target memory cell 11ij is connected to a ground voltage GND through a transistor 31j. As a result, the bit line BLj (or /BLj) corresponding to “L” level is connected to the ground voltage GND through an acceleration circuit AC provided in the memory cell 11ij to thereby accelerate read rate. During data write, the virtual ground line VGj corresponding to the write target bit line pair BLj, /BLj is connected to a power supply voltage VDD through a transistor 33j. As a result, a current is prevented from flowing from the bit line BLj (or /BLj) at “H” level to the virtual ground line VGj and the write rate is not decreased.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.

Abstract: A NAND or NOR content-addressable memory (CAM) cell, which selectively use single port, tow ports, or three ports for operations depending on design requirements. Only n-channel transistors or p-channel transistors design these NAND or NOR CAM cells. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different operations and pruposes.

Abstract: The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

Abstract: The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

Abstract: A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an un-programmed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.

Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

Abstract: A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sense node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison.

Abstract: A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local data lines is associated with one of the memory areas and is connected to a two-wire master data line, common to all the memory areas, by a line circuit-breaker. To represent the binary value of data on a local data line, the wires are driven, to first and second logic potentials. Each line circuit-breaker contains switching devices which, if one of the two wires in the local data line is at the second logic potential, autonomously transfer the potential to the associated wire in the master data line, and, if one of the two wires in the master data line is at the second logic potential, autonomously transfer the potential to the associated wire in the local data line.

Abstract: Memory apparatus and methods are provided for storing data in a semiconductor device, comprising volatile and non-volatile portions, where the non-volatile portion comprises two ferroelectric capacitors coupled with one of two internal nodes in the volatile memory portion. Apparatus is also disclosed wherein first and second ferroelectric capacitors are coupled with the first internal node of the volatile portion, and third and fourth ferroelectric capacitors are coupled with the second internal node of the volatile portion.

Abstract: A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.

Abstract: A high-speed transparent refresh DRAM-based memory cell and architecture are disclosed. Each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.

Abstract: A circuit for sensing a memory cell includes a main cell, a reference cell, a first loading unit for providing a preset voltage to a sensing node of the main cell, a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell, a first switching unit for adjusting the potential of the main cell sensing node, a second switching unit for controlling the potential of the reference cell sensing node, a first voltage controlling unit for adjusting the potential of a bit line of the main cell, a second voltage controlling unit for adjusting the potential of a bit line of the reference cell, and a sense amplifier for sensing a state of the main cell by comparing the potential of the main cell sensing node and that of the reference cell sensing node.

Abstract: A semiconductor integrated circuit device includes a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit. A sense amplifier unit control circuit electrically disconnects sense amplifier circuits from the main memory and data is transferred from the main memory to the auxiliary memory in this disconnected state. A data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to the main memory unit.

Abstract: A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier.

Abstract: Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A magnetic memory device includes a first magnetic tunnel junction having a first reference ferromagnetic layer; a second magnetic tunnel junction having a second reference ferromagnetic layer; and an electrically conductive spacer layer between the first and second reference layers. The first and second reference layers are antiferromagnetically coupled.