Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.

Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver configured to drive the display panel. The panel driver includes a scan on time decider configured to receive line image data for each of the plurality of pixel rows, and to determine a scan on time change amount for each of the plurality of pixel rows based on the line image data, and a scan control block configured to adjust a scan pulse applied to each of the plurality of pixel rows according to the scan on time change amount.

Abstract: Devices and methods include a command interface configured to receive commands, such as a write with an automatic precharge. A bank-specific decoder decodes the write with an automatic precharge command for a corresponding memory bank and outputs a write auto-precharge (WrAP) signal. This WrAP signal has not been adjusted for a write recovery time for the memory bank. Accordingly, bank processing circuitry in a bank receiving the WrAP signal uses the WrAP to cause its internal lockout circuitry to apply a tWR lockout based at least in part on a mode register setting and on the WrAP signal indicating receipt of the write with an automatic precharge command.

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A low-power image capture device includes a first image buffer in SRAM coupled to receive images from an image sensor, and a second image buffer receiving images transferred in bursts from the first image buffer, the second image buffer implemented in PASR DRAM, the image buffers together operating as a first-in, first-out, (FIFO) buffer. The device includes an activation detector. The PASR DRAM is powered while receiving bursts of images from the first image buffer, and when the image capture device is in the activated mode; and in ultra-low power PASR mode otherwise. A method includes capturing images into the first image buffer, transferring the images in bursts into a second image buffer in PASR DRAM powered while receiving the images in bursts, the PASR DRAM otherwise in ultra-low power PASR mode; and, upon activating, an image processor receiving images from the second image buffer.

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract: Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.

Abstract: Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing. An example apparatus may include a memory array comprising a plurality of sense amplifiers. A first sense amplifier is coupled to a first access line segment and to a second access line segment and a second sense amplifier is coupled to a third access line segment and to a load segment. The first, second, and third access line segments are coupled to a respective plurality of memory cells. The load segment comprise load circuitry configured to provide a capacitive load to the second sense amplifier based on a capacitive load of the third access line segment.

Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.

Abstract: Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.

Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, apply an unselected word line signal to unselected word lines and apply a negative pre-pulse signal to the plurality of dummy word lines.

Abstract: A memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.

Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.

Abstract: Apparatuses and methods including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example apparatus includes first and second pull-up transistors coupled to a first power supply node, and first and second pull-down transistors coupled to a second power supply node. A first isolation transistor is coupled to a gate of the second pull-down transistor and to a first sense node to which the first pull-up and first pull-down transistors are also coupled. A second isolation transistor is coupled to a gate of the first pull-down transistor and to a second sense node to which the second pull-up and second pull-down transistors are also coupled. An equalization transistor is coupled to gates of the first and second pull-down transistors, and a precharge transistor is coupled to the second power supply node and to the gate of either the first or second pull-down transistors.

Abstract: A pre-charge circuit of a static random access memory (SRAM) controller and a pre-charging method thereof are provided. The pre-charge circuit of the SRAM controller includes a first switch, a second switch and a third switch. A first terminal of the first switch is coupled to a working voltage, a second terminal of the first switch is coupled to a first bit line of the SRAM controller, and the first switch is controlled by a first turn-on signal. A first terminal of the second switch is coupled to the working voltage, a second terminal of the second switch is coupled to a second bit line of the SRAM controller, and the second switch is controlled by a second turn-on signal. The third switch is coupled between the first bit line and the second bit line, and the third switch is controlled by a third turn-on signal.

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

Abstract: A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.

Abstract: A method for operating a pseudo-dual port (PDP) memory is described. The method includes pre-charging bitline pairs BL and BLB coupled to unselected columns of the PDP memory according to a write operation during a pre-charge operation after a read operation of the PDP memory. The method also includes concurrently pulling-down a bitline pair BL and BLB coupled to a selected column of PDP memory according to the write operation.

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: Memory device provided with a set of memory cells having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: during a start-up phase consecutive to a powering on, applying a first pair of potentials, respectively to the first supply line and the second supply line, in order to pre-load a logic data to some cells depending on the manner in which said cells are respectively connected to said supply lines, then during a second phase, applying a second pair of potentials respectively to said first supply line and the second supply line, so as to symmetrically supply the inverters of each cell.

Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: A channel circuit of source driver and an operation method thereof are provided. The channel circuit includes a digital-to-analog converter (DAC), a first switch, an output buffer circuit and a pre-charge circuit. The terminals of the first switch are coupled to the first output terminal of the DAC and the first input terminal of the output buffer circuit, respectively. The pre-charge circuit is coupled to the first input terminal of the output buffer circuit. The pre-charge circuit pre-charges the first input terminal of the output buffer circuit when the first switch is turned off during a pre-charge period, and not to pre-charge the first input terminal of the output buffer circuit when the first switch is turned on during a normal operation period.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.

Abstract: A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.

Abstract: An operation method of a memory device includes sequentially receiving an active command and a precharge command from an external device, during a first time interval, applying a first activation voltage to a selected wordline in response to the active command, applying a second activation voltage to the selected wordline after the first time interval elapses from a first time point when the first active command is received, and applying a first deactivation voltage to the selected wordline in response to the precharge command. The second activation voltage is lower than the first activation voltage and is higher than the first deactivation voltage.

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

Abstract: A semiconductor device includes: a first switch that uses a first selection signal and a second selection signal to select one of a first voltage and a third voltage or a second voltage and a fourth voltage from the first voltage, the second voltage lower than the first voltage, the third voltage lower than the first voltage, and the fourth voltage lower than the third voltage; a second switch that selects one of a first input signal or a second input signal from the first input signal being the first voltage or the third voltage and the second input signal being the second voltage or the fourth voltage; a third switch that outputs the third voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the first voltage, is selected by the second switch, outputs the first voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the third voltage, is selected by t