Magnetic Patents (Class 365/209)
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Patent number: 11984146Abstract: A neuromorphic device including: a plurality of unit weighting elements connected to a bit line in a manner that shares the bit line, each of the plurality of unit weighting elements being connected to a source line and comprising a fixed layer of which a magnetization direction is fixed, a free layer of which a magnetization direction changes in parallel with or in anti-parallel with the fixed layer, and a tunnel barrier layer arranged between the fixed layer and the free layer and a plurality of drive transistors being selectively turned on according to a plurality of bit selection signals, respectively, and correspondingly driving the unit weighting elements, respectively, wherein the plurality of unit weighting elements have different resistances in such a manner as to correspond to bits, respectively, of a synapse weight.Type: GrantFiled: April 15, 2022Date of Patent: May 14, 2024Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventor: Seung Heon Baek
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Patent number: 11862218Abstract: In some embodiments, the present application provides a memory device. The memory device includes a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows, a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, and a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.Type: GrantFiled: May 19, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gaurav Gupta, Zhiqiang Wu
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Patent number: 11862217Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.Type: GrantFiled: February 15, 2020Date of Patent: January 2, 2024Assignee: TOHOKU UNIVERSITYInventors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
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Patent number: 11474706Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.Type: GrantFiled: April 30, 2013Date of Patent: October 18, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Eric L. Pope, Andrew C. Walton
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Patent number: 11255880Abstract: A voltage detection circuit includes a resistance dividing circuit containing a coarse adjustment variable resistance circuit and a fine adjustment variable resistance circuit, a coarse adjustment circuit controlling the coarse adjustment variable resistance circuit, a fine adjustment circuit controlling the fine adjustment variable resistance circuit, and a control circuit controlling the coarse adjustment circuit and the fine adjustment circuit based upon a detection signal of a comparator circuit.Type: GrantFiled: July 23, 2019Date of Patent: February 22, 2022Assignee: ABLIC INC.Inventor: Yusuke Kanazawa
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Patent number: 11222259Abstract: Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example method includes setting a state of each single bit counter from a set of single bit counters in the crosspoint device, the states of the single bit counters representing the weight to be stored at the crosspoint device. The method further includes adjusting electrical conductance of a resistor device of the crosspoint device. The resistor device includes a set of resistive circuits, each resistive circuit associated with a respective single bit counter from the set of single bit counters, the electrical conductance adjusted by activating or deactivating each resistive circuit according to a state of the associated single bit counter.Type: GrantFiled: December 13, 2017Date of Patent: January 11, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Siyuranga Koswatta, Yulong Li, Paul M. Solomon
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Patent number: 11054466Abstract: A semiconductor device test system and a semiconductor device test method are provided. The system includes a device under test (DUT) which provides an output voltage to a load connected to an output terminal, automatic test equipment (ATE) which supplies power to the DUT and measures the output voltage of the DUT, and a current mirror which is connected between the ATE and the DUT. The ATE outputs a reference current to the current mirror, and the DUT provides an output current to the current mirror. The output current is obtained by mirroring the reference current from the ATE.Type: GrantFiled: May 31, 2018Date of Patent: July 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sung-Gu Lee
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Patent number: 10897592Abstract: A switchable amplifier and comparator circuit includes an operational amplifier having an inverting input, a non-inverting input, a first differential output and a second differential output, the first differential output switchably coupled to the inverting input and the second differential output switchably coupled to the non-inverting input. A first feedback capacitor is coupled to the inverting input and switchably coupled to the first differential output, a second feedback capacitor is coupled to the non-inverting input and switchably coupled to the second differential output. A capacitive load is switchably coupled between the first differential output and the second differential output. A diode clamp circuit is switchably coupled between the first differential output and the second differential output. A resistive load is switchably coupled between the first differential output and the second differential output.Type: GrantFiled: September 16, 2019Date of Patent: January 19, 2021Assignee: Foveon, Inc.Inventors: SundaraSiva Rao Giduturi, Glenn Jay Keller
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Patent number: 10862022Abstract: A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a first magnetic assist layer, a second magnetic assist layer, an antiferromagnetic coupling spacer layer located between the first and second magnetic assist layers, and a first nonmagnetic spacer layer located between the free layer and the first magnetic assist layer. The antiferromagnetic coupling spacer layer is configured to provide antiferromagnetic coupling between a first magnetization direction of the first magnetic assist layer and a second magnetization direction of the second magnetic assist layer.Type: GrantFiled: December 6, 2018Date of Patent: December 8, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Quang Le, Zhanjie Li, Zhigang Bai, Paul Vanderheijden, Michael Ho
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Patent number: 10726352Abstract: Techniques are provided for improving quantum circuits. The technology includes approximately expanding, by a system operatively coupled to a processor, using zero to a number of applications of a super controlled basis gate, a target two-qubit operation, with the approximately expanding resulting in instances of the target two-qubit operation corresponding to the zero to the number of applications, and the target two-qubit operation is part of a source quantum circuit associated with a quantum computer. The system analyzes the instances and the super controlled basis gate, and automatically rewrites the source quantum circuit into a deployed quantum circuit based on the analyzing.Type: GrantFiled: August 14, 2019Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Lev Samuel Bishop
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Patent number: 10423865Abstract: A system and method for paper jam prediction includes a processor, memory and a network interface. Ongoing paper jam data is received from an identified, networked multifunction peripheral. Service call data for the multifunction peripheral indicative of prior service calls is stored in the memory. A sampling window of the paper jam data prior to a service call date is defined and a point in the sampling window when no symptoms of a forthcoming paper jam were present is determined so as to define a prediction window. A relationship between paper jam data in the prediction window of the sampling window and paper jam data outside the prediction window in the sampling window is determined and incoming paper jam data is monitored relative to the relationship data. A paper jam warning is generated when monitored incoming paper jam data indicates a forthcoming paper jam on the multifunction peripheral.Type: GrantFiled: March 6, 2018Date of Patent: September 24, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki KaishaInventors: Michael Yeung, Manju Sreekumar, Milong Sabandith, Methee Phoboonme, Louis Ormond
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Patent number: 10298779Abstract: A method to diagnosis an electro-mechanical part on an image forming device comprises: determining an incident count for a first time interval for the electro-mechanical part; determining if the incident count for the first time interval exceeds a first threshold level; marking the incident count as a high rate if the incident count exceeds the first threshold level; marking the incident count as a low rate if the incident count is more than 0 but equal to or less than the first threshold level; marking the incident count as a zero rate if the incident count is equal to 0; monitoring the electro-mechanical part for a second time interval, wherein the second time interval is a plurality of first time intervals; cumulating a number of first time intervals with the low rate during the second time intervals; and marking the electro-mechanical part as needing to be one of repaired or serviced when the number of first time intervals with the low rate during the second time intervals exceeds a second threshold levelType: GrantFiled: November 20, 2018Date of Patent: May 21, 2019Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Oleg Y Zakharov, Hiroyuki Takaishi
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Patent number: 10158768Abstract: A method to diagnosis an electro-mechanical part on an image forming device comprises: determining an incident count for a first time interval for the electro-mechanical part; determining if the incident count for the first time interval exceeds a first threshold level; marking the incident count as a high rate if the incident count exceeds the first threshold level; marking the incident count as a low rate if the incident count is more than 0 but equal to or less than the first threshold level; marking the incident count as a zero rate if the incident count is equal to 0; monitoring the electro-mechanical part for a second time interval, wherein the second time interval is a plurality of first time intervals; cumulating a number of first time intervals with the low rate during the second time intervals; and marking the electro-mechanical part as needing to be one of repaired or serviced when the number of first time intervals with the low rate during the second time intervals exceeds a second threshold levelType: GrantFiled: July 2, 2018Date of Patent: December 18, 2018Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Oleg Y Zakharov, Hiroyuki Takaishi
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System and method for diagnosing parts of a printing device to be replaced based on an incident rate
Patent number: 10009482Abstract: A method to diagnosis an electro-mechanical part on an image forming device comprises: determining an incident count for a first time interval for the electro-mechanical part; determining if the incident count for the first time interval exceeds a first threshold level; marking the incident count as a high rate if the incident count exceeds the first threshold level; marking the incident count as a low rate if the incident count is more than 0 but equal to or less than the first threshold level; marking the incident count as a zero rate if the incident count is equal to 0; monitoring the electro-mechanical part for a second time interval, wherein the second time interval is a plurality of first time intervals; cumulating a number of first time intervals with the low rate during the second time intervals; and marking the electro-mechanical part as needing to be one of repaired or serviced when the number of first time intervals with the low rate during the second time intervals exceeds a second threshold levelType: GrantFiled: February 28, 2017Date of Patent: June 26, 2018Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Oleg Y. Zakharov, Hiroyuki Takaishi -
Patent number: 9767878Abstract: A method for controlling a magnetic memory device is provided. The method includes: applying a first control signal and a second control signal to a ferromagnetic fixed layer and a ferromagnetic free layer of the magnetic memory device respectively, wherein a first voltage level of the first control signal is lower than a second voltage level of the second control signal; sensing a first current signal flowing through the magnetic memory device; and determining a logical state of a first data bit according to the first current signal.Type: GrantFiled: June 6, 2016Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANT LTD.Inventors: Yu-Der Chih, Tien-Wei Chiang, Chun-Jung Lin, Harry-Hak-Lay Chuang, William J. Gallagher
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Patent number: 9406367Abstract: A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.Type: GrantFiled: September 29, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yue-Der Chih, Kai-Chun Lin, Hung-Chang Yu
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Patent number: 9330756Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.Type: GrantFiled: August 13, 2014Date of Patent: May 3, 2016Assignee: Micron Technology, Inc.Inventor: Ferdinando Bedeschi
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Patent number: 9324421Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.Type: GrantFiled: January 31, 2011Date of Patent: April 26, 2016Assignee: Hewlett Packard Enterprise Development LPInventors: Frederick Perner, Wei Yi, Matthew D. Pickett
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Patent number: 9313052Abstract: A method for receiving signals includes detecting information signal pulses on a first signal transmission channel, generating an output signal dependent on the information signal pulses on the first signal transmission channel, and detecting interference signal pulses on a second signal transmission channel. The second signal transmission channel is open-ended or terminated by a passive component, and interference signal pulses on the first signal transmission channel that occur within a given time window before or after an interference signal pulse on the second signal transmission channel has been detected are ignored and not used for generating the output signal.Type: GrantFiled: January 31, 2008Date of Patent: April 12, 2016Assignee: Infineon Technologies Austria AGInventor: Jose Martinez
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Patent number: 9305629Abstract: An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.Type: GrantFiled: March 15, 2013Date of Patent: April 5, 2016Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
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Patent number: 9202547Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: GrantFiled: March 15, 2013Date of Patent: December 1, 2015Assignee: Intel CorporationInventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
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Patent number: 9165644Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.Type: GrantFiled: May 11, 2012Date of Patent: October 20, 2015Assignees: Axon Technologies Corporation, Adesto Technologies CorporationInventors: Deepak Kamalanathan, Foroozan Sarah Koushan, Juan Pablo Saenz Echeverry, John Dinh, Shane C. Hollmer, Michael Kozicki
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Patent number: 9111606Abstract: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.Type: GrantFiled: December 15, 2014Date of Patent: August 18, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bing Wang
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Patent number: 9065436Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.Type: GrantFiled: December 13, 2013Date of Patent: June 23, 2015Assignee: Intersil Americas LLCInventors: Andrew Joo Kim, Gwilym Luff
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Patent number: 9064548Abstract: A non-volatile register includes register logic connected with first and second ends of a memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.Type: GrantFiled: June 14, 2011Date of Patent: June 23, 2015Assignee: III Holdings 1, LLCInventor: Robert Norman
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Patent number: 9047965Abstract: Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The unselected bit lines and source lines are held at the voltage while separately timed signals pull up or pull down the selected bit lines and source lines during read and write operations.Type: GrantFiled: December 19, 2012Date of Patent: June 2, 2015Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Thomas Andre
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Patent number: 9019746Abstract: A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.Type: GrantFiled: March 16, 2013Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Hyuck-Sang Yim, Taek Sang Song
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Patent number: 8988935Abstract: The present disclosure concerns a method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense and storage layers; the first and second ferromagnetic layers being arranged such that a dipolar coupling between the storage) and the sense layers is substantially null; the method comprising: switching the second ferromagnetic magnetization by passing a spin-polarized current in the magnetic tunnel junction; wherein the spin-polarized current is polarized when passing in the sense layer, in accordance with the direction of the sense magnetization. The MRAM cell can be written with low power consumption.Type: GrantFiled: December 19, 2012Date of Patent: March 24, 2015Assignee: Crocus Technology SAInventors: Ioan Lucian Prejbeanu, Kenneth Mackay
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Patent number: 8953368Abstract: A data reading method of a magnetic memory device includes generating read commands, supplying a read current to a selected magnetic memory element in a first direction and in turn in a second direction under different ones of the read commands, respectively, and sensing the magnitude of the read current flowing through the selected magnetic memory element to read data stored at the selected magnetic memory element.Type: GrantFiled: August 15, 2013Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Soo-Ho Cha
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Patent number: 8953384Abstract: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.Type: GrantFiled: July 31, 2012Date of Patent: February 10, 2015Assignee: Winbond Electronics CorporationInventors: Johnny Chan, Koying Huang
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Patent number: 8949519Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.Type: GrantFiled: July 22, 2009Date of Patent: February 3, 2015Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8947924Abstract: A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result.Type: GrantFiled: June 24, 2011Date of Patent: February 3, 2015Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of SciencesInventors: Xi Li, Houpeng Chen, Zhitang Song, Daolin Cai
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Publication number: 20150029794Abstract: A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with a first node and a second node for currents therethrough to be compared with each other. A cell of the first cell segment and a cell of the second cell segment are coupled to the first nodes of the first and second current sense amplifiers, respectively, and the first and second reference cells are coupled to both the second nodes of the first and second current sense amplifiers.Type: ApplicationFiled: July 23, 2013Publication date: January 29, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: SERGIY ROMANOVSKYY
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Patent number: 8861251Abstract: A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements.Type: GrantFiled: March 19, 2012Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Susumu Shuto
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Patent number: 8848431Abstract: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell.Type: GrantFiled: July 30, 2012Date of Patent: September 30, 2014Assignee: Honeywell International Inc.Inventors: Romney R. Katti, Michael A. Smith
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Patent number: 8724413Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.Type: GrantFiled: September 16, 2011Date of Patent: May 13, 2014Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Mahmud Assar, Parviz Keshtbod
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Publication number: 20140056058Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: Infineon Technologies AGInventors: Mihail Jefremow, Wolf Allers, Jan Otterstedt, Christian Peters, Thomas Kern
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Publication number: 20140056059Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: Infineon Technologies AGInventors: David Mueller, Wolf Allers, Mihail Jefremow
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Patent number: 8634237Abstract: A magnetic memory device comprises a magnetic wire extending in a first direction, a pair of first electrodes operable to pass a current through the magnetic wire in the first direction or in an opposite direction to the first direction, a first insulating layer provided on the magnetic wire in a second direction being substantially perpendicular to the first direction, a plurality of second electrodes provided on the first insulating layer and provided at specified interval in the second direction, and a third electrode electrically connected to the plurality of second electrodes.Type: GrantFiled: March 16, 2012Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura
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Patent number: 8587994Abstract: Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.Type: GrantFiled: July 7, 2011Date of Patent: November 19, 2013Assignee: QUALCOMM IncorporatedInventors: Jung Pill Kim, Tae Hyun Kim
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Patent number: 8400802Abstract: The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design.Type: GrantFiled: November 3, 2010Date of Patent: March 19, 2013Assignee: University-Industry Cooperation Group of Kyunghee UniversityInventors: Sang Hoon Hong, Chang Hoon Han, Min Ah Chae
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Patent number: 8374048Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.Type: GrantFiled: August 11, 2010Date of Patent: February 12, 2013Assignee: Grandis, Inc.Inventor: Dmytro Apalkov
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Patent number: 8338004Abstract: The present invention provides a magnetic tunnel junction structure, including a first magnetic layer having a fixed magnetization direction and a second magnetic layer having a reversible magnetization direction. A non-magnetic layer is formed between the first magnetic layer and the second magnetic layer and a third magnetic layer allows the magnetization direction of the second magnetic layer to be inclined with respect to a plane of the second magnetic layer by a magnetic coupling to the second magnetic layer with a vertical magnetic anisotropic energy thereof larger than a horizontal magnetic anisotropic energy thereof. A crystal-structure separation layer is formed between the second magnetic layer and the third magnetic layer for separating a crystal orientation between the second and the third magnetic layers.Type: GrantFiled: October 29, 2009Date of Patent: December 25, 2012Assignee: Korea Institute of Science and TechnologyInventors: Kyung Ho Shin, Byoung Chul Min
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Patent number: 8331139Abstract: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.Type: GrantFiled: February 28, 2011Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: William J. Gallagher, Daniel C. Worledge
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Patent number: 8320206Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: November 15, 2010Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
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Patent number: 8320166Abstract: A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel to each other, and a second transistor connected in series to each of the second and third MTJ layers, the second transistor having a driving capability corresponding to twice a driving capability of the first transistor of the memory cell.Type: GrantFiled: September 5, 2008Date of Patent: November 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-jun Park, Tae-wan Kim, Sang-jin Park, Dae-jeong Kim, Seung-jun Lee, Hyung-soon Shin
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Patent number: 8270204Abstract: Magnetic shift tracks or magnetic strips, to which application of a rotating magnetic field or by rotation of the strip itself allows accurate determination of domain wall movement. One particular embodiment is a method of determining a position of a domain wall in a magnetic strip. The method includes applying a rotating magnetic field to the magnetic strip, the magnetic field rotating around a longitudinal axis of the magnetic strip, and after applying the magnetic field, determining a displacement of the domain wall to a second position.Type: GrantFiled: July 9, 2009Date of Patent: September 18, 2012Assignee: Seagate Technology LLCInventors: Xiaobin Wang, Haiwen Xi, Yiran Chen, Yuan Yan, Jun Zheng
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Patent number: 8254195Abstract: Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage.Type: GrantFiled: June 1, 2010Date of Patent: August 28, 2012Assignee: QUALCOMM IncorporatedInventor: Hari M. Rao
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Magnetoresistive random access memory (MRAM) with integrated magnetic film enhanced circuit elements
Patent number: 8248840Abstract: A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions.Type: GrantFiled: March 26, 2010Date of Patent: August 21, 2012Assignee: QUALCOMM IncorporatedInventors: Xia Li, Seung H. Kang, Xiaochun Zhu, Kangho Lee -
Patent number: 8244971Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: October 30, 2007Date of Patent: August 14, 2012Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber