Magnetic Patents (Class 365/209)
-
Patent number: 7532533Abstract: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.Type: GrantFiled: April 19, 2007Date of Patent: May 12, 2009Assignee: Everspin Technologies, Inc.Inventors: Thomas W. Andre, Chitra K. Subramanian
-
Patent number: 7511990Abstract: An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.Type: GrantFiled: September 30, 2005Date of Patent: March 31, 2009Assignee: EverSpin Technologies, Inc.Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam
-
Patent number: 7505347Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.Type: GrantFiled: February 28, 2008Date of Patent: March 17, 2009Assignee: Unity Semiconductor CorporationInventors: Darrell Rinerson, Christophe J. Chevallier, Chang Hua Siau
-
Patent number: 7486549Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.Type: GrantFiled: July 10, 2007Date of Patent: February 3, 2009Assignee: Renesas Technology Corp.Inventor: Hideto Hidaka
-
Publication number: 20090010087Abstract: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in.Type: ApplicationFiled: December 28, 2007Publication date: January 8, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Young-Shying CHEN, Chung-Chih WANG, Chia-Pao CHANG, Chien-Chung HUNG
-
Publication number: 20090010088Abstract: A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to the first transistor, a second transmission gate electrically connected to the first and third transistors, a comparison circuit having two input ends respectively connected to the first transistor, and a storage capacitor having an end electrically connected to the first transistor and the other end connected to a power end.Type: ApplicationFiled: December 28, 2007Publication date: January 8, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Young-Shying CHEN, Ding-Yeong WANG
-
Publication number: 20090010044Abstract: A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.Type: ApplicationFiled: February 8, 2006Publication date: January 8, 2009Inventors: Noboru Sakimura, Takeshi Honda, Tadahiko Sugibayashi
-
Patent number: 7436697Abstract: A memory cell having a configuration completely different from that of a memory cell of a conventional memory and having various excellent characteristics, and also a method for manufacturing the same, are provided. A memory having various excellent characteristics is provided as well by use of the memory cell. Furthermore, a method for recording/reading information in/from the memory is provided. The memory cell includes a memory medium for holding information, a controlling part for recording information in the memory medium, and a detecting element for reading information from the memory medium, where the detecting element is provided independently of the memory medium.Type: GrantFiled: March 31, 2004Date of Patent: October 14, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Motoyoshi Murakami, Yasuhiro Gotoh
-
Patent number: 7436698Abstract: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.Type: GrantFiled: December 14, 2006Date of Patent: October 14, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Denny Tang, Li-Shyue Lai, Chao-Hsiung Wang, Fan-Shi Jordan Lai
-
Patent number: 7436723Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.Type: GrantFiled: March 3, 2008Date of Patent: October 14, 2008Inventors: Darrell Rinerson, Christophe J. Chevallier, Chang Hua Siau
-
Patent number: 7433253Abstract: An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.Type: GrantFiled: June 26, 2007Date of Patent: October 7, 2008Assignee: Qimonda AGInventors: Dietmar Gogl, Hans-Heinrich Viehmann
-
Publication number: 20080205129Abstract: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Applicant: MICROMEM TECHNOLOGIES, INC.Inventors: James STEPHENSON, Bruce Shipley, Dan Carothers
-
Patent number: 7414908Abstract: A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding pairs of bit lines at high speed. This is accomplished by a sense amplifier including CMOS inverters cross-connected or connected in loop, a P-channel MOS transistor for shutting the power off during standby, and N-channel MOS transistors for initializing the output of the sense amplifier during standby. A ground terminal of the inverter is connected to a bit line through a transistor of a bit switch, and a ground terminal of the inverter is connected to a bit line through a transistor of a bit switch.Type: GrantFiled: November 30, 2004Date of Patent: August 19, 2008Assignee: International Business Machines CorporationInventors: Hisatada Miyatake, Toshio Sunaga
-
Patent number: 7405966Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.Type: GrantFiled: January 23, 2007Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventors: Mirmajid Seyyedy, Mark E. Tuttle, Glen E. Hush
-
Patent number: 7397694Abstract: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.Type: GrantFiled: January 26, 2006Date of Patent: July 8, 2008Assignee: Industrial Technology Research InstituteInventors: Chi-Ming Chen, Chien-Chung Hung, Young-Shying Chen, Lien-Chang Wang
-
Patent number: 7379364Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.Type: GrantFiled: October 19, 2006Date of Patent: May 27, 2008Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson
-
Patent number: 7376007Abstract: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line.Type: GrantFiled: June 8, 2006Date of Patent: May 20, 2008Assignee: Micromem Technologies, Inc.Inventors: James Stephenson, Bruce Shipley, Dan Carothers
-
Publication number: 20080112214Abstract: A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies. The first electrode is electrically connected to a first portion of a microelectronic assembly (47). The second electrode is electrically connected to a second portion of the microelectronic assembly. The voltage across the first and second portions of the microelectronic assembly is determined based on an electrical resistance of the memory cell. The memory cell may be a magnetoresistive random access memory (MRAM) cell. In one embodiment, the memory cell is a magnetic tunnel junction (MTJ) memory cell.Type: ApplicationFiled: October 30, 2006Publication date: May 15, 2008Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Pon Sung Ku
-
Patent number: 7372753Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.Type: GrantFiled: October 19, 2006Date of Patent: May 13, 2008Inventors: Darrell Rinerson, Christophe Chevallier, Chang Hua Siau
-
Patent number: 7313043Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.Type: GrantFiled: November 29, 2005Date of Patent: December 25, 2007Assignees: Altis Semiconductor SNC, Infineon Technologies AGInventors: Dietmar Gogl, Daniel Braun
-
Patent number: 7313042Abstract: A data bus is precharged to a precharge voltage before data read operation. In the data read operation, the data bus thus precharged is electrically coupled to the same voltage as the precharge voltage through a selected memory cell. A driving transistor couples the data bus to a power supply voltage (driving voltage) in order to supply a sense current in the data read operation. A charge transfer amplifier portion produces an output voltage according to an integral value of the sense current (data read current) flowing through the data bus, while maintaining the data bus at the precharge voltage. A transfer gate, differential amplifier and latch circuit produce read data based on the output voltage sensed at prescribed timing.Type: GrantFiled: December 22, 2005Date of Patent: December 25, 2007Assignee: Renesas Technology Corp.Inventor: Hideto Hidaka
-
Patent number: 7292471Abstract: By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register to one another. By the use of the VCO, the integrating capacitor for the current or the generation of a reference pulse may be eliminated.Type: GrantFiled: March 20, 2006Date of Patent: November 6, 2007Assignee: NEC CorporationInventors: Noboru Sakimura, Takeshi Honda, Tadahiko Sugibayashi
-
Patent number: 7286429Abstract: A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state. The resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state. Differential amplifiers coupled to the memory cell and the high and low reference cells provide a digital output representing the resistance state of the memory cell.Type: GrantFiled: April 24, 2006Date of Patent: October 23, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon Jhy Liaw, Denny Tang
-
Patent number: 7272035Abstract: A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each of the plurality of magnetic storage cells includes a magnetic element and a selection transistor. The magnetic element may be programmed using spin transfer induced switching by a write current driven through the magnetic element. The selection transistor includes a source and a drain. The plurality of magnetic storage cells are grouped in pairs. The source of the selection transistor for one magnetic storage cell of a pair shares the source with the selection transistor for another magnetic storage cell of the pair.Type: GrantFiled: August 31, 2005Date of Patent: September 18, 2007Assignee: Grandis, Inc.Inventors: Eugene Youjun Chen, Yiming Huai
-
Patent number: 7272034Abstract: A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each of the plurality of magnetic storage cells includes at least one magnetic element and a plurality of selection transistors. The at least one magnetic element is capable of being programmed using spin transfer induced switching by a write current driven through the at least one magnetic element. The at least one selection transistor is configured to allow the magnetic element to be alternately selected for writing and reading. Architectures for reading and writing to the magnetic storage cells are also described.Type: GrantFiled: August 31, 2005Date of Patent: September 18, 2007Assignee: Grandis, Inc.Inventors: Eugene Youjun Chen, Yiming Huai
-
Patent number: 7257020Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory celf columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.Type: GrantFiled: September 12, 2006Date of Patent: August 14, 2007Assignee: Renesas Technology Corp.Inventor: Hideto Hidaka
-
Patent number: 7251178Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.Type: GrantFiled: September 7, 2004Date of Patent: July 31, 2007Assignee: Infineon Technologies AGInventors: Dietmar Gogl, Hans-Heinrich Viehmann
-
Patent number: 7245522Abstract: The magnetic memory device comprises: a memory cell including two magnetoresistive effect elements serially connected to each other, and a select transistor connected to a connection node between the two magnetic resistant devices, a bit line connected to the connection node of the magnetoresistive effect elements via the select transistor, and a read circuit for reading information memorized in the magnetoresistive effect elements, based on a voltage of the connection node outputted to the bit line.Type: GrantFiled: March 17, 2005Date of Patent: July 17, 2007Assignee: Fujitsu LimitedInventor: Masaki Aoki
-
Patent number: 7239568Abstract: A magnetic memory cell write current threshold detector. The magnetic memory cell write current threshold detector includes a first MRAM test cell receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell receiving the write current and sensing when the write current exceeds a second threshold.Type: GrantFiled: January 29, 2004Date of Patent: July 3, 2007Assignee: Hewlett-Packard Development Company, LP.Inventors: Frederick A. Perner, Manoj K. Bhattacharyya
-
Patent number: 7233537Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.Type: GrantFiled: October 1, 2002Date of Patent: June 19, 2007Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company LimitedInventors: Hiroaki Tanizaki, Hideto Hidaka, Takaharu Tsuji, Tsukasa Ooishi
-
Patent number: 7224630Abstract: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.Type: GrantFiled: June 24, 2005Date of Patent: May 29, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Thomas W. Andre, Chitra K. Subramanian
-
Patent number: 7203112Abstract: A method or circuit is disclosed for sensing an output of a predetermined memory cell having a high resistance state or a low resistance state. A predefined voltage is applied to the predetermined memory cell to generate an output current reflecting a resistance of the predetermined memory cell, and to one or more reference memory cells to generate a first reference current reflecting the high resistance state, and a second reference current reflecting the low resistance state. A first differential value is provided to represent the difference between the output current and the first reference current. A second differential value is provided to represent the difference between the output current and second reference current. The first differential value with the second differential value to generate a digital output representing the resistance state of the predetermined memory cell.Type: GrantFiled: June 10, 2005Date of Patent: April 10, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jhon Jhy Liaw
-
Patent number: 7187576Abstract: A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer is separated from the fixed layers by insulating layers preferably with different thicknesses, or with different material compositions. The resulting junction resistance can exhibit at least four distinct resistance values dependent on the magnetic orientation of the free magnetic layer. The cell is configured using a pattern with four lobes to store two bits, and eight lobes to store three bits. The resulting cell can be used to provide a fast, non-volatile magnetic random access memory (MRAM) with high density and no need to rewrite stored data after they are read, or as a fast galvanic isolator.Type: GrantFiled: August 25, 2004Date of Patent: March 6, 2007Assignee: Infineon Technologies AGInventors: Daniel Braun, Gerhard Mueller
-
Patent number: 7165197Abstract: In an apparatus for analyzing a magnetic random access memory (MRAM), and a method of analyzing an MRAM, the apparatus includes an MRAM mounting unit on which an MRAM is mounted, a magnetic field applying unit positioned around the MRAM mounting unit for applying an external magnetic field to the MRAM mounted on the MRAM mounting unit, a cell addressing unit for selecting one of a plurality of unit cells of the MRAM mounted on the MRAM mounting unit, a source measurement unit for applying an internal magnetic field to the selected unit cell of the MRAM or for measuring a resistance of the selected unit cell of the MRAM, and a computer unit for storing and for analyzing data regarding the measured resistance of the each of the plurality of unit cells of the MRAM.Type: GrantFiled: November 24, 2004Date of Patent: January 16, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-jun Park, In-jun Hwang, Tae-wan Kim
-
Patent number: 7154773Abstract: An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a non-magnetic tunneling barrier layer. The first magnetic region includes a reference layer having a fixed magnetization adjacent the tunneling barrier layer. The second magnetic region includes a free layer having first and second free magnetizations aligned with an easy axis of magnetization of the free layer. The first and second free magnetizations are oppositely aligned and separated by a magnetic domain wall. The magnetic domain wall is magnetically movable along the easy axis of the free layer, and the free layer is magnetically coupled to magnetic fields generated by first and second currents running through first and second conductive lines crossing each other, wherein the easy axis of the free layer is inclined under an inclination angle relative to both the first and second conductive lines.Type: GrantFiled: March 31, 2005Date of Patent: December 26, 2006Assignee: Infineon Technologies AGInventors: Daniel Braun, Gerhard Mueller
-
Patent number: 7154798Abstract: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.Type: GrantFiled: April 27, 2005Date of Patent: December 26, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny Tang, Li-Shyue Lai, Chao-Hsiung Wang, Fang-Shi Jordan Lai
-
Patent number: 7145796Abstract: A semiconductor integrated circuit device includes a magneto-resistive effect element and a plug. The magneto-resistive effect element includes a first magnetic layer whose magnetization direction is fixed and a second magnetic layer whose magnetization direction can be changed. The plug is formed to penetrate through the second magnetic layer in the film thickness direction of the second magnetic layer and used to apply a write magnetic field to the second magnetic layer.Type: GrantFiled: September 3, 2004Date of Patent: December 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Hiroaki Yoda
-
Patent number: 7113422Abstract: A method to adjust an operating parameter of a magnetoresistive random access memory having a tunable circuit, such as a bias control circuit, provides for measuring the operating parameter, such as a word current or sense current, of the magnetoresistive random access memory to obtain a measured operating parameter result and tuning the tunable circuit, such as with trimmable resistors, based on the measured operating parameter result. A method is also provided to adjust an operating parameter of a wafer of magnetic random access memories each having a tunable circuit by measuring the operating parameter one or more of the magnetic random access memories to obtain a measured operating parameter result and tuning some or all of the tunable circuits based on the measured operating parameter result.Type: GrantFiled: November 30, 2003Date of Patent: September 26, 2006Assignee: Union Semiconductor Technology CorporationInventor: Wayne Theel
-
Patent number: 7110312Abstract: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line.Type: GrantFiled: October 19, 2001Date of Patent: September 19, 2006Assignee: Micromem Technologies Inc.Inventors: James Stephenson, Bruce Shipley, Dan Carothers
-
Patent number: 7102922Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.Type: GrantFiled: June 28, 2005Date of Patent: September 5, 2006Assignee: Renesas Technology Corp.Inventor: Hideto Hidaka
-
Patent number: 7102917Abstract: An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control, a shared switched voltage line that is capable of applying a voltage to the voltage divider inputs of the memory cell strings in the set, a common bit-sense line operatively coupled to the bit-sense outputs of the memory cell strings, a bit-sense output control line that is capable of selectively connecting the bit-sense output of a memory cell string to the common bit-sense line, and a ground operatively coupled to the voltage divider grounds of the voltage divider grounds.Type: GrantFiled: September 3, 2004Date of Patent: September 5, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Frederick A. Perner
-
Patent number: 7102948Abstract: An embodiment includes a resistance change sensor. The resistance change sensor includes a first input connected to a first resistance and a second input connected to a second resistance. The sensor further includes a resistance detector for sensing a resistive change in at least one of the first resistance and the second resistance.Type: GrantFiled: April 1, 2004Date of Patent: September 5, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Frederick A. Perner
-
Patent number: 7082050Abstract: A magnetic random access memory (10) with equalization has a plurality of magnetic memory elements that perform a memory operation. A word line magnetically activates at least one magnetic memory element. A sense line detects the state of the at least one magnetic memory element. A word line driver is connected to the word line to drive a current on the word line during the memory operation. A word line equalizer is connected to the word line to equalize the word line during the non-memory operations.Type: GrantFiled: November 30, 2003Date of Patent: July 25, 2006Assignee: Union Semiconductor Technology CorporationInventor: Wayne Theel
-
Patent number: 7079436Abstract: Embodiments of the present invention provide a resistive cross point memory. The resistive cross point memory comprises an array of memory cells and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and calibrate the read circuit based on the sensed result. The read circuit comprises an up/down counter that provides a calibration value to the read circuit.Type: GrantFiled: September 30, 2003Date of Patent: July 18, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, Kenneth Kay Smith
-
Patent number: 7079414Abstract: A memory cell array is constructed by two-dimensionally arranging a plurality of memory cells each composed of a magnetoresistive element, in a row and column directions. Write word lines are provided along the row direction of the memory cell array. Write bit lines are provided along the column direction of the memory cell array. To write data, a pulse-like write current is applied to an appropriate word and bit lines to generate magnetic fields in the column and row directions. A combined magnetic field of the magnetic fields in the column and row directions is applied to a memory cell to write data. A control circuit controls the pulse width of the pulse-like write current applied to the word and bit lines so that the pulse width has a predetermined temperature dependence.Type: GrantFiled: January 28, 2004Date of Patent: July 18, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Iwata, Yuui Shimizu
-
Patent number: 7057925Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.Type: GrantFiled: January 31, 2005Date of Patent: June 6, 2006Assignee: Renesas Technology Corp.Inventors: Tsukasa Ooishi, Hideto Hidaka
-
Patent number: 7054185Abstract: A word current source (445) for a magnetoresistive random access memory circuit (420) includes an n-channel transistor (430) including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the magnetoresistive random access memory circuit. A positive supply voltage is coupled to the magnetoresistive random access memory circuit (420) so as to allow current to flow through the magnetoresistive random access memory circuit (420) when an activation signal is applied to the gate by the control circuit.Type: GrantFiled: November 30, 2003Date of Patent: May 30, 2006Assignee: Union Semiconductor Technology CorporationInventor: Wayne Theel
-
Patent number: 7042036Abstract: A method for implementing miniaturization of magnetic random access memory (MRAM) and a magnetic memory using single domain switching by direct current are provided. The magnetic memory preferably includes a half-circle or U-shaped architecture with an exchange biasing pad, such as a FeMn exchange biasing pad that effectively generates a head-to-head magnetization configuration. The magnetic memory also includes nanometer scale notches in order to minimize magnetostatic interaction between a single domain memory element and the spin current sources and to effectively trap the magnetic domain wall. Reading the bit can be carried out by anisotropic magnetoresistance, or by other means of determining the magnetization orientation through resistance measurements, such as a spin valve or a magnetic tunneling junction.Type: GrantFiled: August 5, 2004Date of Patent: May 9, 2006Assignee: The University of ChicagoInventors: Seok-Hwan Chung, Axel F. Hoffmann
-
Patent number: 7042783Abstract: One embodiment of a magnetic memory includes a memory cell configured to provide a first state, and a sensing circuit. The sensing circuit is configured to charge a capacitor through the memory cell in the first state and discharge the capacitor through the memory cell in the first state to determine a state of the memory cell.Type: GrantFiled: June 18, 2003Date of Patent: May 9, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard Lee Hilton
-
Patent number: 7042753Abstract: A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR element is held between the local interconnection wire and a bit line. The TMR element is constituted by stacked TMR layers. Each TMR layer is able to have two states, that is, a state in which spin directions are parallel and anti-parallel. Therefore, the TMR element stores four-value data. A current-driving line is set immediately below the TMR element.Type: GrantFiled: February 13, 2002Date of Patent: May 9, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Fumio Horiguchi